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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
| commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
| tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/opt/opt_const.cc | |
| parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 85e4c4c1..0fcacf0a 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -589,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec b = cell->getPort("\\B"); if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { - int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); + int width = max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); } |