diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-06-09 18:07:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-09 18:07:05 +0200 |
| commit | a75b249427923c7f3ea604c5748291bdba25d1d0 (patch) | |
| tree | 35620b13ce3aa5b85936575c95b2841aac0fba90 /passes/sat/example.ys | |
| parent | b210234612beb3e20d5338d03debf084c9b6c7b9 (diff) | |
Implemented temporal induction proofs in sat_solve
Diffstat (limited to 'passes/sat/example.ys')
| -rw-r--r-- | passes/sat/example.ys | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys index 19f8f50e..c532c1fb 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,11 +1,13 @@ + read_verilog example.v proc; opt_clean + sat_solve -set y 1'b1 example001 sat_solve -set y 1'b1 example002 sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 sat_solve -set y 1'b1 example004 sat_solve -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 -sat_solve -prove y 1'b0 example001 -# sat_solve -show rst,counter -prove y 1'b0 -set-at 1 rst 1'b1 -seq 1 example004 +sat_solve -prove y 1'b0 -show rst,counter,y example004 +sat_solve -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 |