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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-08 09:34:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-08 09:34:36 +0200 |
| commit | c681c17038acb5f60d5abcf58f20d6a8d2bdffef (patch) | |
| tree | 173fad143fab6fa573bc4ad1493bda1084538c49 /passes/sat/example.ys | |
| parent | 56b593b91cc693849e3b3b3de0666f6ec9a597f6 (diff) | |
Improved auto-detection of -show signals in sat_solve
Diffstat (limited to 'passes/sat/example.ys')
| -rw-r--r-- | passes/sat/example.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys index e2eb1749..b6d131c9 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,3 +1,3 @@ read_verilog example.v techmap; opt; abc; opt -sat_solve -show a -set y 1'b1 +sat_solve -set y 1'b1 |