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authorClifford Wolf <clifford@clifford.at>2015-08-14 11:27:19 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-14 11:27:19 +0200
commit03500748192dc93583c0e0f95640865603650714 (patch)
treeca2a7fda2451656a9be78763ac741d6e14253c3d /passes/techmap
parent84bf862f7c58c2b69babf043ff5032f924a3ee4d (diff)
Re-created command-reference-manual.tex, copied some doc fixes to online help
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/extract.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 3c24524d..68a7fc1f 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -361,7 +361,7 @@ struct ExtractPass : public Pass {
log("\n");
log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
log("in the given map file and replaces them with instances of this modules. The\n");
- log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
+ log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n");
log("\n");
log(" -map <map_file>\n");
log(" use the modules in this file as reference. This option can be used\n");