diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
| commit | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (patch) | |
| tree | bcee5a22fc9ac7dca5b871ce667114e5f15d07d0 /passes/techmap | |
| parent | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (diff) | |
Added module->design and cell->module, wire->module pointers
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index ed389f2f..060a8740 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -724,7 +724,7 @@ struct ExtractPass : public Pass { RTLIL::Module *newMod = new RTLIL::Module; newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); - map->modules_[newMod->name] = newMod; + map->add(newMod); int portCounter = 1; for (auto wire : wires) { |