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author | Clifford Wolf <clifford@clifford.at> | 2014-02-07 17:44:57 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-07 17:44:57 +0100 |
commit | fc3b3c4ec3955b165166d9f44965fac0e1879505 (patch) | |
tree | 2552ece4d6e1709f7ef17d838b00f7f774faf95b /techlibs/common/simlib.v | |
parent | a1ac710ab8740ae781e0274f63633e8ed2650da4 (diff) |
Added $slice and $concat cell types
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 87e83bd1..4436abfe 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -829,6 +829,36 @@ endmodule // -------------------------------------------------------- +module \$slice (A, Y); + +parameter OFFSET = 0; +parameter A_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +output [Y_WIDTH-1:0] Y; + +assign Y = A >> OFFSET; + +endmodule + +// -------------------------------------------------------- + +module \$concat (A, B, Y); + +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [A_WIDTH+B_WIDTH-1:0] Y; + +assign Y = {B, A}; + +endmodule + +// -------------------------------------------------------- + module \$mux (A, B, S, Y); parameter WIDTH = 0; |