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author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
commit | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch) | |
tree | 4c438282926d7bac304ad3ad6ad89523c4c1d784 /techlibs/intel/common | |
parent | db3c67fd6e140893450a44870ee9a75dd1f48b27 (diff) |
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'techlibs/intel/common')
-rw-r--r-- | techlibs/intel/common/brams_map.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v index fae4af2a..d0f07c1d 100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map.v @@ -2,8 +2,8 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A parameter CFG_ABITS = 8; parameter CFG_DBITS = 36; - parameter ABITS = "1"; - parameter DBITS = "1"; + parameter ABITS = 1; + parameter DBITS = 1; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; @@ -63,21 +63,21 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A .width_byteena_a (1), // Forced value .numwords_b ( NUMWORDS ), .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_ABITS ), - .width_b ( CFG_DBITS ), - .widthad_a ( CFG_ABITS ), - .width_a ( CFG_DBITS ) + .widthad_b ( CFG_DBITS ), + .width_b ( CFG_ABITS ), + .widthad_a ( CFG_DBITS ), + .width_a ( CFG_ABITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), .wren_a(B1EN), .rden_a(A1EN), .q_a(A1DATA), - .data_b(1'b0), + .data_b(B1DATA), .address_b(0), .wren_b(1'b0), .rden_b(1'b0), - .q_b(1'b0), + .q_b(), .clock0(CLK2), .clock1(1'b1), // Unused in single port mode .clocken0(1'b1), |