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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-26 22:29:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-26 22:29:40 +0200 |
| commit | d635f8adaa40ca1e52c5da7b71d70284d6aef7dc (patch) | |
| tree | 4738fa8de602cb2228c1c9ff9a5fe51a0ba8f071 /techlibs/xilinx/cells.v | |
| parent | 4007b41d40147bf3d282f25f6c177a17fb2a8f76 (diff) | |
Renamed techlibs/xilinx7 to techlibs/xilinx
Diffstat (limited to 'techlibs/xilinx/cells.v')
| -rw-r--r-- | techlibs/xilinx/cells.v | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v new file mode 100644 index 00000000..8c8b9c75 --- /dev/null +++ b/techlibs/xilinx/cells.v @@ -0,0 +1,53 @@ +module \$_DFF_P_ (D, C, Q); + + input D, C; + output Q; + + FDRE fpga_dff ( + .D(D), .Q(Q), .C(C), + .CE(1'b1), .R(1'b0) + ); + +endmodule + +module \$lut (I, O); + + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] I; + output O; + + generate + if (WIDTH == 1) begin:lut1 + LUT1 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0])); + end else + if (WIDTH == 2) begin:lut2 + LUT2 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1])); + end else + if (WIDTH == 3) begin:lut3 + LUT3 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2])); + end else + if (WIDTH == 4) begin:lut4 + LUT4 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3])); + end else + if (WIDTH == 5) begin:lut5 + LUT5 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3]), .I4(I[4])); + end else + if (WIDTH == 6) begin:lut6 + LUT6 #(.INIT(LUT)) fpga_lut (.O(O), + .I0(I[0]), .I1(I[1]), .I2(I[2]), + .I3(I[3]), .I4(I[4]), .I5(I[5])); + end else begin:error + wire TECHMAP_FAIL; + end + endgenerate + +endmodule |