initial import

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diff --git a/tests/asicworld/code_hdl_models_dff_async_reset.v b/tests/asicworld/code_hdl_models_dff_async_reset.v
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+++ b/tests/asicworld/code_hdl_models_dff_async_reset.v
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+//-----------------------------------------------------
+// Design Name : dff_async_reset
+// File Name   : dff_async_reset.v
+// Function    : D flip-flop async reset
+// Coder       : Deepak Kumar Tala
+//-----------------------------------------------------
+module dff_async_reset (
+data  , // Data Input
+clk    , // Clock Input
+reset , // Reset input 
+q         // Q output
+);
+//-----------Input Ports---------------
+input data, clk, reset ; 
+
+//-----------Output Ports---------------
+output q;
+
+//------------Internal Variables--------
+reg q;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk or negedge reset)
+if (~reset) begin
+  q <= 1'b0;
+end  else begin
+  q <= data;
+end
+
+endmodule //End Of Module dff_async_reset