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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_hdl_models_mux_using_case.v |
initial import
Diffstat (limited to 'tests/asicworld/code_hdl_models_mux_using_case.v')
-rw-r--r-- | tests/asicworld/code_hdl_models_mux_using_case.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/asicworld/code_hdl_models_mux_using_case.v b/tests/asicworld/code_hdl_models_mux_using_case.v new file mode 100644 index 00000000..123da448 --- /dev/null +++ b/tests/asicworld/code_hdl_models_mux_using_case.v @@ -0,0 +1,28 @@ +//----------------------------------------------------- +// Design Name : mux_using_case +// File Name : mux_using_case.v +// Function : 2:1 Mux using Case +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module mux_using_case( +din_0 , // Mux first input +din_1 , // Mux Second input +sel , // Select input +mux_out // Mux output +); +//-----------Input Ports--------------- +input din_0, din_1, sel ; +//-----------Output Ports--------------- +output mux_out; +//------------Internal Variables-------- +reg mux_out; +//-------------Code Starts Here--------- +always @ (sel or din_0 or din_1) +begin : MUX + case(sel ) + 1'b0 : mux_out = din_0; + 1'b1 : mux_out = din_1; + endcase +end + +endmodule //End Of Module mux |