initial import

1 files changed, 18 insertions, 0 deletions

diff --git a/tests/asicworld/code_tidbits_asyn_reset.v b/tests/asicworld/code_tidbits_asyn_reset.v
new file mode 100644
index 00000000..58e47c56
--- /dev/null
+++ b/tests/asicworld/code_tidbits_asyn_reset.v
@@ -0,0 +1,18 @@
+module  asyn_reset(clk,reset,a,c);
+     input clk;
+     input reset;
+     input a;
+     output c; 
+
+   wire clk;
+   wire reset;   
+   wire a;    
+   reg c;
+        
+always @ (posedge clk or posedge reset)
+ if ( reset == 1'b1) begin
+   c <= 0;
+ end else begin
+   c <= a;
+ end
+endmodule