initial import

1 files changed, 15 insertions, 0 deletions

diff --git a/tests/asicworld/code_tidbits_reg_seq_example.v b/tests/asicworld/code_tidbits_reg_seq_example.v
new file mode 100644
index 00000000..458c8792
--- /dev/null
+++ b/tests/asicworld/code_tidbits_reg_seq_example.v
@@ -0,0 +1,15 @@
+module reg_seq_example( clk, reset, d, q);
+input clk, reset, d;
+output q;
+  
+reg   q;
+wire clk, reset, d;
+
+always @ (posedge clk or posedge reset)
+if (reset) begin
+  q <= 1'b0;
+end else begin
+  q <= d;
+end
+
+endmodule