initial import

1 files changed, 14 insertions, 0 deletions

diff --git a/tests/asicworld/code_verilog_tutorial_d_ff.v b/tests/asicworld/code_verilog_tutorial_d_ff.v
new file mode 100644
index 00000000..7a408360
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_d_ff.v
@@ -0,0 +1,14 @@
+// D flip-flop Code
+module d_ff ( d, clk, q, q_bar);
+input d ,clk;
+output q, q_bar;
+wire d ,clk;
+reg q, q_bar;
+  	 
+always @ (posedge clk)
+begin
+  q <= d;
+  q_bar <= !d;
+end
+
+endmodule