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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
| commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
| tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_verilog_tutorial_decoder_always.v | |
initial import
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_decoder_always.v')
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_decoder_always.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_decoder_always.v b/tests/asicworld/code_verilog_tutorial_decoder_always.v new file mode 100644 index 00000000..4418ec70 --- /dev/null +++ b/tests/asicworld/code_verilog_tutorial_decoder_always.v @@ -0,0 +1,20 @@ +module decoder_always (in,out); +input [2:0] in; +output [7:0] out; +reg [7:0] out; + +always @ (in) +begin + out = 0; + case (in) + 3'b001 : out = 8'b0000_0001; + 3'b010 : out = 8'b0000_0010; + 3'b011 : out = 8'b0000_0100; + 3'b100 : out = 8'b0000_1000; + 3'b101 : out = 8'b0001_0000; + 3'b110 : out = 8'b0100_0000; + 3'b111 : out = 8'b1000_0000; + endcase +end + +endmodule |