initial import

1 files changed, 24 insertions, 0 deletions

diff --git a/tests/asicworld/code_verilog_tutorial_v2k_reg.v b/tests/asicworld/code_verilog_tutorial_v2k_reg.v
new file mode 100644
index 00000000..537a9e85
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_v2k_reg.v
@@ -0,0 +1,24 @@
+module v2k_reg();
+
+// v2k allows to init variables
+reg a = 0;
+// Here only last variable is set to 0, i.e d = 0
+// Rest b, c are set to x
+reg b, c, d = 0;
+// reg data type can be signed in v2k
+// We can assign with signed constants
+reg signed [7:0] data = 8'shF0;
+
+// Function can return signed values
+// Its ports can contain signed ports
+function signed [7:0] adder;
+  input a_in;
+  input b_in;
+  input c_in;
+  input signed [7:0] data_in;
+  begin
+    adder = a_in + b_in + c_in + data_in;
+  end
+endfunction
+
+endmodule