Added test cases from 2012 paper on comparison of foss verilog synthesis tools

1 files changed, 20 insertions, 0 deletions

diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v
new file mode 100644
index 00000000..70ee7e66
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+++ b/tests/simple/forgen01.v
@@ -0,0 +1,20 @@
+module uut_forgen01(a, y);
+
+input [4:0] a;
+output y;
+
+integer i, j;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule