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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
| commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
| tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/simple/usb_phy_tetsts.v | |
initial import
Diffstat (limited to 'tests/simple/usb_phy_tetsts.v')
| -rw-r--r-- | tests/simple/usb_phy_tetsts.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/simple/usb_phy_tetsts.v b/tests/simple/usb_phy_tetsts.v new file mode 100644 index 00000000..2375183d --- /dev/null +++ b/tests/simple/usb_phy_tetsts.v @@ -0,0 +1,36 @@ + +// from usb_rx_phy +module test01(clk, rst, rx_en, fs_ce); + +input clk, rst; +input rx_en; +output reg fs_ce; +reg [1:0] dpll_next_state; +reg [1:0] dpll_state; + +always @(posedge clk) + dpll_state <= rst ? 0 : dpll_next_state; + +always @* + begin + fs_ce = 1'b0; + case(dpll_state) + 2'h0: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h1; + 2'h1:begin + fs_ce = 1'b1; + if(rx_en) dpll_next_state = 2'h3; + else dpll_next_state = 2'h2; + end + 2'h2: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h3; + 2'h3: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h0; + endcase + end + +endmodule + |