diff options
195 files changed, 729 insertions, 729 deletions
@@ -63,7 +63,7 @@ There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for more information: - http://www.clifford.at/yosys/download.html + http://www.clifford.at/yosys/download.html To configure the build system to use a specific compiler, use one of diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index af6f8726..8d13a26d 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/btor/README b/backends/btor/README index fcfe1482..efcf0d8f 100644 --- a/backends/btor/README +++ b/backends/btor/README @@ -6,7 +6,7 @@ Master git repository for the BTOR backend: https://github.com/ahmedirfan1983/yosys -[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking +[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking Johannes Kepler University, Linz, Austria http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 079a82a2..cd050314 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -3,11 +3,11 @@ * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2014 Ahmed Irfan <irfan@fbk.eu> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -18,7 +18,7 @@ * */ -// [[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking +// [[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking // Johannes Kepler University, Linz, Austria // http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf @@ -75,10 +75,10 @@ struct BtorDumper std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file int line_num;//last line number of btor file std::string str;//temp string for writing file - std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers + std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers RTLIL::IdString curr_cell; //current cell being dumped std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation - std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write + std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) : f(f), module(module), design(design), config(config), ct(design), sigmap(module) { @@ -143,7 +143,7 @@ struct BtorDumper //concat cell_type_translation["$concat"] = "concat"; - //signed cell type translation + //signed cell type translation //binary s_cell_type_translation["$modx"] = "srem"; s_cell_type_translation["$mody"] = "smod"; @@ -152,9 +152,9 @@ struct BtorDumper s_cell_type_translation["$le"] = "slte"; s_cell_type_translation["$gt"] = "sgt"; s_cell_type_translation["$ge"] = "sgte"; - + } - + vector<shared_str> cstr_buf; const char *cstr(const RTLIL::IdString id) @@ -166,17 +166,17 @@ struct BtorDumper cstr_buf.push_back(str); return cstr_buf.back().c_str(); } - + int dump_wire(RTLIL::Wire* wire) { if(basic_wires[wire->name]) - { + { log("writing wire %s\n", cstr(wire->name)); auto it = line_ref.find(wire->name); if(it==std::end(line_ref)) { ++line_num; - line_ref[wire->name]=line_num; + line_ref[wire->name]=line_num; str = stringf("%d var %d %s", line_num, wire->width, cstr(wire->name)); f << stringf("%s\n", str.c_str()); return line_num; @@ -200,7 +200,7 @@ struct BtorDumper log(" -- found cell %s\n", cstr(cell_id)); RTLIL::Cell* cell = module->cells_.at(cell_id); const RTLIL::SigSpec* cell_output = get_cell_output(cell); - int cell_line = dump_cell(cell); + int cell_line = dump_cell(cell); if(dep_set.size()==1 && wire->width == cell_output->size()) { @@ -235,7 +235,7 @@ struct BtorDumper } if(dep_set.size()==0) { - log(" - checking sigmap\n"); + log(" - checking sigmap\n"); RTLIL::SigSpec s = RTLIL::SigSpec(wire); wire_line = dump_sigspec(&s, s.size()); line_ref[wire->name]=wire_line; @@ -243,16 +243,16 @@ struct BtorDumper line_ref[wire->name]=wire_line; return wire_line; } - else + else { - log(" -- already processed wire\n"); + log(" -- already processed wire\n"); return it->second; } } log_abort(); return -1; } - + int dump_memory(const RTLIL::Memory* memory) { log("writing memory %s\n", cstr(memory->name)); @@ -262,7 +262,7 @@ struct BtorDumper ++line_num; int address_bits = ceil(log(memory->size)/log(2)); str = stringf("%d array %d %d", line_num, memory->width, address_bits); - line_ref[memory->name]=line_num; + line_ref[memory->name]=line_num; f << stringf("%s\n", str.c_str()); return line_num; } @@ -300,7 +300,7 @@ struct BtorDumper f << stringf("%s\n", str.c_str()); } ++line_num; - str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1); + str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1); f << stringf("%s\n", str.c_str()); return 1; } @@ -326,11 +326,11 @@ struct BtorDumper return line_num; } else - log("writing const error\n"); + log("writing const error\n"); log_abort(); return -1; } - + int dump_sigchunk(const RTLIL::SigChunk* chunk) { log("writing sigchunk\n"); @@ -338,21 +338,21 @@ struct BtorDumper if(chunk->wire == NULL) { RTLIL::Const data_const(chunk->data); - l=dump_const(&data_const, chunk->width, chunk->offset); + l=dump_const(&data_const, chunk->width, chunk->offset); } else { if (chunk->width == chunk->wire->width && chunk->offset == 0) l = dump_wire(chunk->wire); - else + else { int wire_line_num = dump_wire(chunk->wire); log_assert(wire_line_num>0); ++line_num; - str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num, + str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num, chunk->width + chunk->offset - 1, chunk->offset); f << stringf("%s\n", str.c_str()); - l = line_num; + l = line_num; } } return l; @@ -369,8 +369,8 @@ struct BtorDumper if (s.is_chunk()) { l = dump_sigchunk(&s.chunks().front()); - } - else + } + else { int l1, l2, w1, w2; l1 = dump_sigchunk(&s.chunks().front()); @@ -395,7 +395,7 @@ struct BtorDumper { l = it->second; } - + if (expected_width != s.size()) { log(" - changing width of sigspec\n"); @@ -422,7 +422,7 @@ struct BtorDumper log_assert(l>0); return l; } - + int dump_cell(const RTLIL::Cell* cell) { auto it = line_ref.find(cell->name); @@ -466,10 +466,10 @@ struct BtorDumper int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); w = w>output_width ? w:output_width; //padding of w - int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w); + int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w); int cell_line = l; if(cell->type != "$pos") - { + { cell_line = ++line_num; bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true; str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l); @@ -481,7 +481,7 @@ struct BtorDumper str = stringf ("%d slice %d %d %d %d;4", line_num, output_width, cell_line, output_width-1, 0); f << stringf("%s\n", str.c_str()); cell_line = line_num; - } + } line_ref[cell->name]=cell_line; } else if(cell->type == "$reduce_xnor" || cell->type == "$logic_not")//no direct translation in btor @@ -502,7 +502,7 @@ struct BtorDumper ++line_num; str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_xor").c_str(), output_width, l); f << stringf("%s\n", str.c_str()); - } + } ++line_num; str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, l); f << stringf("%s\n", str.c_str()); @@ -510,7 +510,7 @@ struct BtorDumper } //binary cells else if(cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || - cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || + cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt" ) { log("writing binary cell - %s\n", cstr(cell->type)); @@ -521,15 +521,15 @@ struct BtorDumper bool l2_signed YS_ATTRIBUTE(unused) = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool(); int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); - + log_assert(l1_signed == l2_signed); - l1_width = l1_width > output_width ? l1_width : output_width; + l1_width = l1_width > output_width ? l1_width : output_width; l1_width = l1_width > l2_width ? l1_width : l2_width; l2_width = l2_width > l1_width ? l2_width : l1_width; int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width); int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width); - + ++line_num; std::string op = cell_type_translation.at(cell->type.str()); if(cell->type == "$lt" || cell->type == "$le" || @@ -539,13 +539,13 @@ struct BtorDumper if(l1_signed) op = s_cell_type_translation.at(cell->type.str()); } - + str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2); f << stringf("%s\n", str.c_str()); line_ref[cell->name]=line_num; } - else if(cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || + else if(cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" ) { //TODO: division by zero case @@ -555,15 +555,15 @@ struct BtorDumper bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool(); int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); - + log_assert(l1_signed == l2_signed); - l1_width = l1_width > output_width ? l1_width : output_width; + l1_width = l1_width > output_width ? l1_width : output_width; l1_width = l1_width > l2_width ? l1_width : l2_width; l2_width = l2_width > l1_width ? l2_width : l1_width; int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width); int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width); - + ++line_num; std::string op = cell_type_translation.at(cell->type.str()); if(cell->type == "$div" && l1_signed) @@ -631,7 +631,7 @@ struct BtorDumper f << stringf("%s\n", str.c_str()); cell_output = line_num; } - line_ref[cell->name] = cell_output; + line_ref[cell->name] = cell_output; } else if(cell->type == "$logic_and" || cell->type == "$logic_or")//no direct translation in btor { @@ -678,7 +678,7 @@ struct BtorDumper int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width); int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1); ++line_num; - str = stringf ("%d %s %d %d %d %d", + str = stringf ("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1); //if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell f << stringf("%s\n", str.c_str()); @@ -693,7 +693,7 @@ struct BtorDumper int cases = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width*select_width); int select = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), select_width); int *c = new int[select_width]; - + for (int i=0; i<select_width; ++i) { ++line_num; @@ -701,15 +701,15 @@ struct BtorDumper f << stringf("%s\n", str.c_str()); c[i] = line_num; ++line_num; - str = stringf ("%d slice %d %d %d %d", line_num, output_width, cases, i*output_width+output_width-1, + str = stringf ("%d slice %d %d %d %d", line_num, output_width, cases, i*output_width+output_width-1, i*output_width); f << stringf("%s\n", str.c_str()); } - + ++line_num; str = stringf ("%d cond %d %d %d %d", line_num, output_width, c[select_width-1], c[select_width-1]+1, default_case); f << stringf("%s\n", str.c_str()); - + for (int i=select_width-2; i>=0; --i) { ++line_num; @@ -741,7 +741,7 @@ struct BtorDumper { start_bit+=output_width; slice = ++line_num; - str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1, + str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1, start_bit-output_width); f << stringf("%s\n", str.c_str()); } @@ -753,16 +753,16 @@ struct BtorDumper output_width); bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool(); ++line_num; - str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(), - output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-", + str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(), + output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-", sync_reset_value, slice); f << stringf("%s\n", str.c_str()); slice = line_num; } ++line_num; - str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), + str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), output_width, polarity?"":"-", cond, slice, reg); - + f << stringf("%s\n", str.c_str()); int next = line_num; if(cell->type == "$adff") @@ -772,12 +772,12 @@ struct BtorDumper int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")), output_width, 0); ++line_num; - str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), + str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), output_width, async_reset_pol ? "":"-", async_reset, async_reset_value, next); f << stringf("%s\n", str.c_str()); } ++line_num; - str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), + str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, reg, next); f << stringf("%s\n", str.c_str()); } @@ -795,7 +795,7 @@ struct BtorDumper int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width); int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); ++line_num; - str = stringf("%d read %d %d %d", line_num, data_width, mem, address); + str = stringf("%d read %d %d %d", line_num, data_width, mem, address); f << stringf("%s\n", str.c_str()); line_ref[cell->name]=line_num; } @@ -829,7 +829,7 @@ struct BtorDumper f << stringf("%s\n", str.c_str()); mem = line_num - 1; } - */ + */ ++line_num; if(polarity) str = stringf("%d one 1", line_num); @@ -837,21 +837,21 @@ struct BtorDumper str = stringf("%d zero 1", line_num); f << stringf("%s\n", str.c_str()); ++line_num; - str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1); + str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1); f << stringf("%s\n", str.c_str()); ++line_num; - str = stringf("%d and 1 %d %d", line_num, line_num-1, enable); + str = stringf("%d and 1 %d %d", line_num, line_num-1, enable); f << stringf("%s\n", str.c_str()); ++line_num; - str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data); + str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data); f << stringf("%s\n", str.c_str()); /* ++line_num; - str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem); - f << stringf("%s\n", str.c_str()); + str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem); + f << stringf("%s\n", str.c_str()); ++line_num; - str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1); - f << stringf("%s\n", str.c_str()); + str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1); + f << stringf("%s\n", str.c_str()); */ mem_next[mem].insert(std::make_pair(line_num-1, line_num)); } @@ -865,11 +865,11 @@ struct BtorDumper const RTLIL::SigSpec* output YS_ATTRIBUTE(unused) = &cell->getPort(RTLIL::IdString("\\Y")); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); log_assert(output->size() == output_width); - int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int(); + int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int(); ++line_num; str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset); - f << stringf("%s\n", str.c_str()); - line_ref[cell->name]=line_num; + f << stringf("%s\n", str.c_str()); + line_ref[cell->name]=line_num; } else if(cell->type == "$concat") { @@ -883,10 +883,10 @@ struct BtorDumper log_assert(input_b->size() == input_b_width); int input_b_line = dump_sigspec(input_b, input_b_width); ++line_num; - str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, - input_a_line, input_b_line); - f << stringf("%s\n", str.c_str()); - line_ref[cell->name]=line_num; + str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, + input_a_line, input_b_line); + f << stringf("%s\n", str.c_str()); + line_ref[cell->name]=line_num; } curr_cell.clear(); return line_num; @@ -912,7 +912,7 @@ struct BtorDumper { output_sig = &cell->getPort(RTLIL::IdString("\\Q")); } - else + else { output_sig = &cell->getPort(RTLIL::IdString("\\Y")); } @@ -930,7 +930,7 @@ struct BtorDumper void dump() { f << stringf(";module %s\n", cstr(module->name)); - + log("creating intermediate wires map\n"); //creating map of intermediate wires as output of some cell for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) @@ -966,7 +966,7 @@ struct BtorDumper basic_wires[wire_id] = true; } } - else + else { for(unsigned i=0; i<output_sig->chunks().size(); ++i) { @@ -976,11 +976,11 @@ struct BtorDumper } } } - + log("writing input\n"); std::map<int, RTLIL::Wire*> inputs, outputs; std::vector<RTLIL::Wire*> safety; - + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input) @@ -998,7 +998,7 @@ struct BtorDumper dump_wire(wire); } f << stringf("\n"); - + log("writing memories\n"); for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it) { @@ -1014,9 +1014,9 @@ struct BtorDumper log("writing cells\n"); for(auto cell_it = module->cells_.begin(); cell_it != module->cells_.end(); ++cell_it) { - dump_cell(cell_it->second); + dump_cell(cell_it->second); } - + log("writing memory next"); for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it) { @@ -1027,7 +1027,7 @@ struct BtorDumper dump_property(it); f << stringf("\n"); - + log("writing outputs info\n"); f << stringf(";outputs\n"); for (auto &it : outputs) { @@ -1047,7 +1047,7 @@ struct BtorDumper struct BtorBackend : public Backend { BtorBackend() : Backend("btor", "write design to BTOR file") { } - + virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -1069,7 +1069,7 @@ struct BtorBackend : public Backend { size_t argidx=1; extra_args(f, filename, args, argidx); - + if (top_module_name.empty()) for (auto & mod_it:design->modules_) if (mod_it.second->get_bool_attribute("\\top")) @@ -1079,7 +1079,7 @@ struct BtorBackend : public Backend { *f << stringf("; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str); *f << stringf("; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n"); *f << stringf(";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"); - + std::vector<RTLIL::Module*> mod_list; for (auto module_it : design->modules_) diff --git a/backends/btor/verilog2btor.sh b/backends/btor/verilog2btor.sh index abe31b9b..cfdc066a 100755 --- a/backends/btor/verilog2btor.sh +++ b/backends/btor/verilog2btor.sh @@ -17,11 +17,11 @@ FULL_PATH=$(readlink -f $1) DIR=$(dirname $FULL_PATH) ./yosys -q -p " -read_verilog -sv $1; -hierarchy -top $3; -hierarchy -libdir $DIR; -hierarchy -check; -proc; +read_verilog -sv $1; +hierarchy -top $3; +hierarchy -libdir $DIR; +hierarchy -check; +proc; opt; opt_const -mux_undef; opt; rename -hide;;; #techmap -map +/pmux2mux.v;; @@ -29,7 +29,7 @@ splice; opt; memory_dff -wr_only; memory_collect;; flatten;; -memory_unpack; +memory_unpack; splitnets -driver; setundef -zero -undriven; opt;;; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index b089be14..475e43da 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 814d3e8f..adabf05e 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -492,5 +492,5 @@ struct DumpPass : public Pass { } } } DumpPass; - + PRIVATE_NAMESPACE_END diff --git a/backends/ilang/ilang_backend.h b/backends/ilang/ilang_backend.h index 159cd719..97dcbb62 100644 --- a/backends/ilang/ilang_backend.h +++ b/backends/ilang/ilang_backend.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 6d4731e7..72a70e38 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -159,7 +159,7 @@ struct IntersynthBackend : public Backend { } } - // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types + // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; diff --git a/backends/json/json.cc b/backends/json/json.cc index 59158cfa..388251e3 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index b485b4eb..4f3b2319 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 9e304dae..f4e8ff72 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 2c614178..12e2c669 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -120,7 +120,7 @@ struct SpiceBackend : public Backend { log("Write the current design to an SPICE netlist file.\n"); log("\n"); log(" -big_endian\n"); - log(" generate multi-bit ports in MSB first order \n"); + log(" generate multi-bit ports in MSB first order\n"); log(" (default is LSB first)\n"); log("\n"); log(" -neg net_name\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d160ec03..9b806461 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -967,7 +967,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } // Output verilog that looks something like this: - // reg [..] _3_; + // reg [..] _3_; // always @(posedge CLK2) begin // _3_ <= memory[D1ADDR]; // if (A1EN) @@ -1011,7 +1011,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - + // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_ // FIXME: $sr, $dlatch, $memrd, $memwr, $fsm diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0b63248d..b93a53d2 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -555,7 +555,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) children[1]->dumpVlog(f, ""); fprintf(f, "}}"); break; - + if (0) { case AST_BIT_NOT: txt = "~"; } if (0) { case AST_REDUCE_AND: txt = "&"; } if (0) { case AST_REDUCE_OR: txt = "|"; } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d57e91e5..69bbc813 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index e566d653..e241142d 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 8ed8c673..ae538c54 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 88df28f8..5b09ad04 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -383,7 +383,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, detect_width_simple = true; child_0_is_self_determined = true; break; - + case AST_MEMRD: detect_width_simple = true; children_are_self_determined = true; diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index d09c63d8..4bf05074 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/blif/blifparse.h b/frontends/blif/blifparse.h index 1da36e00..4d7f59d6 100644 --- a/frontends/blif/blifparse.h +++ b/frontends/blif/blifparse.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc index 7a4687a3..7361a254 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/ilang/ilang_frontend.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ilang/ilang_frontend.h b/frontends/ilang/ilang_frontend.h index b04d6c51..ad3ffec9 100644 --- a/frontends/ilang/ilang_frontend.h +++ b/frontends/ilang/ilang_frontend.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index ace992fb..57296403 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index 4661d577..2139f91f 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 464c5c94..f02a7323 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -40,7 +40,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& if (id_len == 0) log_error("Expected identifier at `%s'.\n", expr); - + if (id_len == 1 && (*expr == '0' || *expr == '1')) return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5f362a0c..ce975358 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -947,6 +947,6 @@ struct VerificPass : public Pass { } #endif } VerificPass; - + YOSYS_NAMESPACE_END diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 735bc5f9..5dc149df 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index e2118630..fb8a7b95 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -109,7 +109,7 @@ static std::string next_token(bool pass_newline = false) } return token; } - + if (ch == ' ' || ch == '\t') { while ((ch = next_char()) != 0) { diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 416b89bd..91bc807f 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 5561f54c..fb98f4af 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8fbaa953..48039153 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d935cab3..0a6a6111 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -1054,13 +1054,13 @@ behavioral_stmt: }; case_type: - TOK_CASE { + TOK_CASE { case_type_stack.push_back(0); } | - TOK_CASEX { + TOK_CASEX { case_type_stack.push_back('x'); } | - TOK_CASEZ { + TOK_CASEZ { case_type_stack.push_back('z'); }; diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 82ff7b50..80bf243f 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -178,6 +178,6 @@ struct Vhdl2verilogPass : public Pass { log_pop(); } } Vhdl2verilogPass; - + YOSYS_NAMESPACE_END diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 00bbc3bf..288571d9 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -154,7 +154,7 @@ struct BitPatternPool { return database.empty(); } -}; +}; YOSYS_NAMESPACE_END diff --git a/kernel/calc.cc b/kernel/calc.cc index 99980e92..32c06c18 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 5b1e618f..be2e7bbb 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/cellaigs.h b/kernel/cellaigs.h index f548f466..1417a614 100644 --- a/kernel/cellaigs.h +++ b/kernel/cellaigs.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/celltypes.h b/kernel/celltypes.h index afdbda5d..229f80b7 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/consteval.h b/kernel/consteval.h index c2e9710f..4d48b45e 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/cost.h b/kernel/cost.h index c6c631e0..4f12889f 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/driver.cc b/kernel/driver.cc index dda27c6a..ce40425d 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/hashlib.h b/kernel/hashlib.h index bb7afd78..2f847950 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -1,5 +1,5 @@ // This is free and unencumbered software released into the public domain. -// +// // Anyone is free to copy, modify, publish, use, compile, sell, or // distribute this software, either in source code form or as a compiled // binary, for any purpose, commercial or non-commercial, and by any diff --git a/kernel/log.cc b/kernel/log.cc index 91d85772..4f395c75 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/log.h b/kernel/log.h index abd20404..b113b567 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/macc.h b/kernel/macc.h index cac5b00d..7efd0228 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/modtools.h b/kernel/modtools.h index 69c13bd3..44c1bde1 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/register.cc b/kernel/register.cc index d3b21c46..179d064f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -659,7 +659,7 @@ struct HelpPass : public Pass { help(); } } HelpPass; - + struct EchoPass : public Pass { EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } virtual void help() @@ -704,6 +704,6 @@ struct MinisatSatSolver : public SatSolver { return new ezMiniSAT(); } } MinisatSatSolver; - + YOSYS_NAMESPACE_END diff --git a/kernel/register.h b/kernel/register.h index 0a10483f..0ef07b76 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index cc7b1a7b..c497ee10 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -2870,7 +2870,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) if (width_ > width) remove(width, width_ - width); - + if (width_ < width) { RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; if (!is_signed) @@ -3439,7 +3439,7 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const for (auto &it : cases) new_switchrule->cases.push_back(it->clone()); return new_switchrule; - + } RTLIL::SyncRule *RTLIL::SyncRule::clone() const @@ -3471,7 +3471,7 @@ RTLIL::Process *RTLIL::Process::clone() const for (auto &it : syncs) new_proc->syncs.push_back(it->clone()); - + return new_proc; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 854ec130..bf39d0f0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -209,7 +209,7 @@ namespace RTLIL char operator[](size_t i) const { const char *p = c_str(); - for (; i != 0; i--, p++) + for (; i != 0; i--, p++) log_assert(*p != 0); return *p; } @@ -954,25 +954,25 @@ public: RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addReduceAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addReduceOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addReduceXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addShl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addShr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addSshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addSshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addShift (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addShiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addLt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addEq (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); @@ -981,21 +981,21 @@ public: RTLIL::Cell* addNex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addGe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addGt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addAdd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addSub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addMul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addDiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addMod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addPow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false); - + RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - + RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); - + RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset); RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addLut (RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut); diff --git a/kernel/satgen.h b/kernel/satgen.h index 719b0a83..7b099444 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/sigtools.h b/kernel/sigtools.h index f92a87db..7082ace4 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/utils.h b/kernel/utils.h index 2ec6182e..8942905f 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -186,7 +186,7 @@ struct TopoSort active_stack.pop_back(); active_cells.erase(n); } - + marked_cells.insert(n); sorted.push_back(n); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index d66f33b1..2e4d5672 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/kernel/yosys.h b/kernel/yosys.h index d4f46a51..6aacd4d5 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/demo_bit.cc b/libs/ezsat/demo_bit.cc index 2a5099bf..c7b11246 100644 --- a/libs/ezsat/demo_bit.cc +++ b/libs/ezsat/demo_bit.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/demo_cmp.cc b/libs/ezsat/demo_cmp.cc index b2df8a8d..8d7ceb2b 100644 --- a/libs/ezsat/demo_cmp.cc +++ b/libs/ezsat/demo_cmp.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/demo_vec.cc b/libs/ezsat/demo_vec.cc index b994f00d..eb8d7599 100644 --- a/libs/ezsat/demo_vec.cc +++ b/libs/ezsat/demo_vec.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/ezminisat.cc b/libs/ezsat/ezminisat.cc index dee82a8d..e0ee6292 100644 --- a/libs/ezsat/ezminisat.cc +++ b/libs/ezsat/ezminisat.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/ezminisat.h b/libs/ezsat/ezminisat.h index 5b5252d8..983e6fd0 100644 --- a/libs/ezsat/ezminisat.h +++ b/libs/ezsat/ezminisat.h @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 8d232f33..da36fb74 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -1373,7 +1373,7 @@ int ezSAT::manyhot(const std::vector<int> &vec, int min_hot, int max_hot) if (max_hot < 0) max_hot = min_hot; - + std::vector<int> formula; int M = max_hot+1, N = vec.size(); std::map<std::pair<int,int>, int> x; diff --git a/libs/ezsat/ezsat.h b/libs/ezsat/ezsat.h index 0faaa6b8..78e125bf 100644 --- a/libs/ezsat/ezsat.h +++ b/libs/ezsat/ezsat.h @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/ezsat/puzzle3d.cc b/libs/ezsat/puzzle3d.cc index aee0044b..59f840f9 100644 --- a/libs/ezsat/puzzle3d.cc +++ b/libs/ezsat/puzzle3d.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -253,7 +253,7 @@ int main() } for (size_t i = 1; i < vecvec.size(); i++) ez.assume(ez.ordered(vecvec[0], vecvec[1])); - + printf("Found and eliminated %d spatial symmetries.\n", int(symmetries.size())); printf("Generated %d clauses over %d variables.\n", ez.numCnfClauses(), ez.numCnfVariables()); diff --git a/libs/ezsat/testbench.cc b/libs/ezsat/testbench.cc index d20258c3..d6dc41fa 100644 --- a/libs/ezsat/testbench.cc +++ b/libs/ezsat/testbench.cc @@ -2,11 +2,11 @@ * ezSAT -- A simple and easy to use CNF generator for SAT solvers * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -220,12 +220,12 @@ void test_count(uint32_t x) fprintf(stderr, "FAILED 6bit-no-clipping test!\n"); abort(); } - + if (cv4 != sat.vec_count(v, 4, true)) { fprintf(stderr, "FAILED 4bit-clipping test!\n"); abort(); } - + printf("ok.\n"); } diff --git a/libs/subcircuit/README b/libs/subcircuit/README index 757a9f54..b1335681 100644 --- a/libs/subcircuit/README +++ b/libs/subcircuit/README @@ -330,7 +330,7 @@ Mining for frequent SubCircuits The solver also contains a miner for frequent subcircuits. The following code fragment will find all frequent subcircuits with at least minNodes nodes and -at most maxNodes nodes that occurs at least minMatches times: +at most maxNodes nodes that occurs at least minMatches times: std::vector<SubCircuit::Solver::MineResult> results; mySolver.mine(results, minNodes, maxNodes, minMatches); @@ -370,7 +370,7 @@ This package also contains a small command-line tool called "scshell" that can be used for experimentation with the algorithm. This program reads a series of commands from stdin and reports its findings to stdout on exit. - $ ./scshell < test_macc22.txt + $ ./scshell < test_macc22.txt ... diff --git a/libs/subcircuit/subcircuit.cc b/libs/subcircuit/subcircuit.cc index cf14df0a..7c723683 100644 --- a/libs/subcircuit/subcircuit.cc +++ b/libs/subcircuit/subcircuit.cc @@ -3,11 +3,11 @@ * algorithm for coarse grain logic networks * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/libs/subcircuit/subcircuit.h b/libs/subcircuit/subcircuit.h index d673af88..5291c642 100644 --- a/libs/subcircuit/subcircuit.h +++ b/libs/subcircuit/subcircuit.h @@ -3,11 +3,11 @@ * algorithm for coarse grain logic networks * * Copyright (C) 2013 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -115,7 +115,7 @@ namespace SubCircuit private: SolverWorker *worker; - + protected: virtual bool userCompareNodes(const std::string &needleGraphId, const std::string &needleNodeId, void *needleUserData, const std::string &haystackGraphId, const std::string &haystackNodeId, void *haystackUserData, const std::map<std::string, std::string> &portMapping); diff --git a/libs/subcircuit/test_large.spl b/libs/subcircuit/test_large.spl index 74a47d94..e33e2698 100644 --- a/libs/subcircuit/test_large.spl +++ b/libs/subcircuit/test_large.spl @@ -99,7 +99,7 @@ function makeGraph(seed, gates, primaryInputs, primaryOutputs) foreach netDecl (unusedOutpus) push primaryOutputs, netDecl; - + return code; } diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 0f521fb0..3e36fa38 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -150,11 +150,11 @@ write_blif softusb_navre.blif \end{figure} The first and last line obviously read the Verilog file and write the BLIF -file. +file. \medskip -The 2nd line checks the design hierarchy and instantiates parametrized +The 2nd line checks the design hierarchy and instantiates parametrized versions of the modules in the design, if necessary. In the case of this simple design this is a no-op. However, as a general rule a synthesis script should always contain this command as first command after reading the input @@ -174,7 +174,7 @@ instead of {\tt opt}. \item The command {\tt proc} converts {\it processes} (Yosys' internal representation of Verilog {\tt always}- and {\tt initial}-blocks) to circuits of multiplexers and storage elements (various types of flip-flops). -\item The command {\tt memory} converts Yosys' internal representations of +\item The command {\tt memory} converts Yosys' internal representations of arrays and array accesses to multi-port block memories, and then maps this block memories to address decoders and flip-flops, unless the option {\tt -nomap} is used, in which case the multi-port block memories stay in the design diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex index 504ab7ec..b9a8237f 100644 --- a/manual/APPNOTE_011_Design_Investigation.tex +++ b/manual/APPNOTE_011_Design_Investigation.tex @@ -256,7 +256,7 @@ Verilog file containing blackbox modules. There are two ways to load cell descriptions into Yosys: First the Verilog file for the cell library can be passed directly to the {\tt show} command using the {\tt -lib <filename>} option. Secondly it is possible to load cell libraries into the design with -the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great +the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great advantage that the library only needs to be loaded once and can then be used in all subsequent calls to the {\tt show} command. @@ -296,7 +296,7 @@ In addition to {\it what\/} to display one also needs to carefully decide {\it when\/} to display it, with respect to the synthesis flow. In general it is a good idea to troubleshoot a circuit in the earliest state in which a problem can be reproduced. So if, for example, the internal state before calling -the {\tt techmap} command already fails to verify, it is better to troubleshoot +the {\tt techmap} command already fails to verify, it is better to troubleshoot the coarse-grain version of the circuit before {\tt techmap} than the gate-level circuit after {\tt techmap}. @@ -316,7 +316,7 @@ yosys> ls 1 modules: example -yosys> cd example +yosys> cd example yosys [example]> ls @@ -708,7 +708,7 @@ For example (see Fig.~\ref{submod} for the circuit diagram of {\tt selstage}): {\scriptsize \begin{verbatim} yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1 - + 9. Executing EVAL pass (evaluate the circuit given an input). Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1 Eval result: \n2 = 2'10. @@ -729,10 +729,10 @@ The {\tt -table} option can be used to create a truth table. For example: {\scriptsize \begin{verbatim} yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0] - + 10. Executing EVAL pass (evaluate the circuit given an input). Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0] - + \s1 \d [0] | \n1 \n2 ---- ------ | ---- ---- 2'00 1'0 | 2'00 2'00 @@ -743,7 +743,7 @@ The {\tt -table} option can be used to create a truth table. For example: 2'10 1'1 | 2'xx 2'10 2'11 1'0 | 2'00 2'00 2'11 1'1 | 2'xx 2'11 - + Assumend undef (x) value for the following singals: \s2 \end{verbatim} } @@ -780,11 +780,11 @@ Final proof equation: \ok = 1'1 Solving problem with 2790 variables and 8241 clauses.. SAT proof finished - model found: FAIL! - ______ ___ ___ _ _ _ _ + ______ ___ ___ _ _ _ _ (_____ \ / __) / __) (_) | | | | _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | | | ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_| - | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ + | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ |_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_| @@ -811,15 +811,15 @@ Final proof equation: \ok = 1'1 Solving problem with 2790 variables and 8257 clauses.. SAT proof finished - no model found: SUCCESS! - /$$$$$$ /$$$$$$$$ /$$$$$$$ - /$$__ $$ | $$_____/ | $$__ $$ - | $$ \ $$ | $$ | $$ \ $$ - | $$ | $$ | $$$$$ | $$ | $$ - | $$ | $$ | $$__/ | $$ | $$ - | $$/$$ $$ | $$ | $$ | $$ + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ - \__/ + \__/ \end{lstlisting} \caption{Experiments with the miter circuit from Fig.~\ref{primetest}. The first attempt of proving that 31 is prime failed because the SAT solver found a creative way of factorizing 31 using integer overflow.} @@ -840,20 +840,20 @@ corresponding input values. For Example: {\scriptsize \begin{verbatim} yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001 - + 11. Executing SAT pass (solving SAT problems in the circuit). Full command line: sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001 - + Setting up SAT problem: Import set-constraint: \s1 = \s2 Import set-constraint: { \n2 \n1 } = 4'1001 Final constraint equation: { \n2 \n1 \s1 } = { 4'1001 \s2 } Imported 3 cells to SAT database. Import show expression: { \s1 \s2 \d } - + Solving problem with 81 variables and 207 clauses.. SAT solving finished - model found: - + Signal Name Dec Hex Bin -------------------- ---------- ---------- --------------- \d 9 9 1001 diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index 5a7c5b19..67f15bc2 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -182,7 +182,7 @@ file: \begin{figure}[H] \begin{lstlisting}[language=sh,numbers=none] -$ boolector fsm.btor +$ boolector fsm.btor unsat \end{lstlisting} \renewcommand{\figurename}{Listing} @@ -204,16 +204,16 @@ executed by {\tt verilog2btor.sh}. \begin{figure}[H] \begin{lstlisting}[language=sh] -read_verilog -sv $1; -hierarchy -top $3; hierarchy -libdir $DIR; -hierarchy -check; -proc; opt; +read_verilog -sv $1; +hierarchy -top $3; hierarchy -libdir $DIR; +hierarchy -check; +proc; opt; opt_const -mux_undef; opt; rename -hide;;; splice; opt; memory_dff -wr_only; memory_collect;; flatten;; -memory_unpack; +memory_unpack; splitnets -driver; setundef -zero -undriven; opt;;; @@ -242,7 +242,7 @@ line: collecting the memories to multi-port memories. \item Flattening the design to get only one module. \item Separating read and write memories. -\item Splitting the signals that are partially assigned +\item Splitting the signals that are partially assigned \item Setting undef to zero value. \item Final optimization pass. \item Writing BTOR file. @@ -259,10 +259,10 @@ modified Yosys script file: \begin{figure}[H] \begin{lstlisting}[language=sh,numbers=none] -read_verilog -sv $1; -hierarchy -top $3; hierarchy -libdir $DIR; -hierarchy -check; -proc; opt; +read_verilog -sv $1; +hierarchy -top $3; hierarchy -libdir $DIR; +hierarchy -check; +proc; opt; opt_const -mux_undef; opt; rename -hide;;; splice; opt; @@ -294,7 +294,7 @@ module array(input clk); mem[counter] <= counter; end - assert property (!(counter > 8'd0) || + assert property (!(counter > 8'd0) || mem[counter - 8'd1] == counter - 8'd1); endmodule @@ -422,7 +422,7 @@ Robert Brummayer and Armin Biere and Florian Lonsing, BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking\\ \url{http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf} -\bibitem{nuxmv} +\bibitem{nuxmv} Roberto Cavada and Alessandro Cimatti and Michele Dorigatti and Alberto Griggio and Alessandro Mariotti and Andrea Micheli and Sergio Mover and Marco Roveri and Stefano Tonetta, The nuXmv Symbolic Model diff --git a/manual/CHAPTER_Appnotes.tex b/manual/CHAPTER_Appnotes.tex index 2abfa85d..6f03b79c 100644 --- a/manual/CHAPTER_Appnotes.tex +++ b/manual/CHAPTER_Appnotes.tex @@ -5,7 +5,7 @@ % \begin{fixme} % This appendix will cover some typical use-cases of Yosys in the form of application notes. % \end{fixme} -% +% % \section{Synthesizing using a Cell Library in Liberty Format} % \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist} % \section{Reconfigurable Coarse-Grain Synthesis using Intersynth} diff --git a/manual/CHAPTER_Basics.tex b/manual/CHAPTER_Basics.tex index c0eda0e8..2f7ea0d6 100644 --- a/manual/CHAPTER_Basics.tex +++ b/manual/CHAPTER_Basics.tex @@ -56,8 +56,8 @@ and how they relate to different kinds of synthesis. Regardless of the way a lower level representation of a circuit is obtained (synthesis or manual design), the lower level representation is usually verified by comparing simulation results of the lower level and the higher level -representation \footnote{In recent years formal equivalence -checking also became an important verification method for validating RTL and +representation \footnote{In recent years formal equivalence +checking also became an important verification method for validating RTL and lower abstraction representation of the design.}. Therefore even if no synthesis is used, there must still be a simulatable representation of the circuit in all levels to allow for verification of the @@ -270,7 +270,7 @@ signals. \subsection{Expressions in Verilog} -In all situations where Verilog accepts a constant value or signal name, +In all situations where Verilog accepts a constant value or signal name, expressions using arithmetic operations such as \lstinline[language=Verilog]{+}, \lstinline[language=Verilog]{-} and \lstinline[language=Verilog]{*}, boolean operations such as @@ -470,7 +470,7 @@ optimizes the design. First of all because not all optimizations are applicable designs and all synthesis tasks. Some optimizations work (best) on a coarse-grained level (with complex cells such as adders or multipliers) and others work (best) on a fine-grained level (single bit gates). Some optimizations target area and others target speed. -Some work well on large designs while others don't scale well and can only be applied +Some work well on large designs while others don't scale well and can only be applied to small designs. A good tool is capable of applying a wide range of optimizations at different diff --git a/manual/CHAPTER_Eval/grep-it.sh b/manual/CHAPTER_Eval/grep-it.sh index f92eb52c..0f4f95ae 100644 --- a/manual/CHAPTER_Eval/grep-it.sh +++ b/manual/CHAPTER_Eval/grep-it.sh @@ -79,6 +79,6 @@ done # if [ $luts -gt 0 -a $luts_ys -gt 0 ]; then luts_p=$(( 100*luts_ys / luts )); else luts_p=NaN; fi # if [ $freq -gt 0 -a $freq_ys -gt 0 ]; then freq_p=$(( 100*freq_ys / freq )); else freq_p=NaN; fi # printf '%-30s %3s %3s %3s\n' $mod $regs_p $luts_p $freq_p -# +# # done diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex index f735d46b..76e5d847 100644 --- a/manual/CHAPTER_Intro.tex +++ b/manual/CHAPTER_Intro.tex @@ -35,7 +35,7 @@ The proposed custom HDL synthesis tool should be licensed under a Free and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis tool would have been needed as basis to build upon. The main advantages of choosing Verilog or VHDL is the ability to synthesize existing HDL code and -to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, +to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool would have to provide a feature-complete implementation of the synthesizable HDL subset. @@ -68,7 +68,7 @@ problem of implementing a HDL synthesis tool is approached in the case of Yosys. Chapter~\ref{chapter:overview} contains a more detailed overview of the -implementation of Yosys. This chapter covers the data structures used in +implementation of Yosys. This chapter covers the data structures used in Yosys to represent a design in detail and is therefore recommended reading for everyone who is interested in understanding the Yosys internals. @@ -81,7 +81,7 @@ is recommended reading for everyone who actually wants to read or write Yosys source code. The chapter concludes with an example loadable module for Yosys. -Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} +Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} cover three important pieces of the synthesis pipeline: The Verilog frontend, the optimization passes and the technology mapping to the target architecture, respectively. diff --git a/manual/CHAPTER_Optimize.tex b/manual/CHAPTER_Optimize.tex index af8e2249..58636a61 100644 --- a/manual/CHAPTER_Optimize.tex +++ b/manual/CHAPTER_Optimize.tex @@ -241,7 +241,7 @@ by identifying the driver for the state signal. From there the {\tt \$mux}-tree driving the state register inputs is recursively traversed. All select inputs are control signals and the leaves of the -{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf +{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf that is not the state signal itself is found. The list of control outputs is initialized with the bits from the state signal. diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index ec402231..645acd2d 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -307,11 +307,11 @@ process $proc$ff_with_en_and_async_reset.v:4$1 switch \reset case 1'1 assign $0\q[0:0] 1'0 - case + case switch \enable case 1'1 assign $0\q[0:0] \d - case + case end end sync posedge \clock @@ -338,7 +338,7 @@ An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a container for zero or more RTLIL::CaseRule objects. -In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first +In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first assigned the old value {\tt \textbackslash{}q} as default value (line 2). The root case also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object is very similar to the C {\tt switch} statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine @@ -371,7 +371,7 @@ process $proc$ff_with_en_and_async_reset.v:4$1 switch \enable case 1'1 assign $0\q[0:0] \d - case + case end sync posedge \clock update \q $0\q[0:0] @@ -449,7 +449,7 @@ See Sec.~\ref{sec:memcells} for details about the memory cell types. Yosys reads and processes commands from synthesis scripts, command line arguments and an interactive command prompt. Yosys commands consist of a command name and an optional whitespace separated list of arguments. Commands are terminated using the newline character -or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored. +or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored. See Sec.~\ref{sec:typusecase} for an example synthesis script. The command {\tt help} can be used to access the command reference manual. diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 4849c6a7..b2428a67 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -1,5 +1,5 @@ // This is free and unencumbered software released into the public domain. -// +// // Anyone is free to copy, modify, publish, use, compile, sell, or // distribute this software, either in source code form or as a compiled // binary, for any purpose, commercial or non-commercial, and by any diff --git a/manual/CHAPTER_StateOfTheArt/simlib_hana.v b/manual/CHAPTER_StateOfTheArt/simlib_hana.v index fc82f138..7fb54fa4 100644 --- a/manual/CHAPTER_StateOfTheArt/simlib_hana.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_hana.v @@ -1,4 +1,4 @@ -/* +/* Copyright (C) 2009-2010 Parvez Ahmad Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>. @@ -45,7 +45,7 @@ module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ∈ endmodule - + module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ∈ @@ -63,7 +63,7 @@ module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = |in; endmodule - + module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = |in; @@ -82,7 +82,7 @@ module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~∈ endmodule - + module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~∈ @@ -100,7 +100,7 @@ module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~|in; endmodule - + module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~|in; @@ -119,7 +119,7 @@ module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ^in; endmodule - + module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ^in; @@ -138,7 +138,7 @@ module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~^in; endmodule - + module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~^in; @@ -156,7 +156,7 @@ always @(in or enable) 1'b1 : out = 2'b10; endcase end -endmodule +endmodule module DEC2 (input [1:0] in, input enable, output reg [3:0] out); @@ -171,7 +171,7 @@ always @(in or enable) 2'b11 : out = 4'b1000; endcase end -endmodule +endmodule module DEC3 (input [2:0] in, input enable, output reg [7:0] out); @@ -190,7 +190,7 @@ always @(in or enable) 3'b111 : out = 8'b10000000; endcase end -endmodule +endmodule module DEC4 (input [3:0] in, input enable, output reg [15:0] out); @@ -217,7 +217,7 @@ always @(in or enable) 4'b1111 : out = 16'b1000000000000000; endcase end -endmodule +endmodule module DEC5 (input [4:0] in, input enable, output reg [31:0] out); always @(in or enable) @@ -259,7 +259,7 @@ always @(in or enable) 5'b11111 : out = 32'b10000000000000000000000000000000; endcase end -endmodule +endmodule module DEC6 (input [5:0] in, input enable, output reg [63:0] out); @@ -335,7 +335,7 @@ always @(in or enable) 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase end -endmodule +endmodule module MUX2(input [1:0] in, input select, output reg out); @@ -345,7 +345,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule module MUX4(input [3:0] in, input [1:0] select, output reg out); @@ -357,7 +357,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule module MUX8(input [7:0] in, input [2:0] select, output reg out); @@ -373,7 +373,7 @@ always @( in or select) 6: out = in[6]; 7: out = in[7]; endcase -endmodule +endmodule module MUX16(input [15:0] in, input [3:0] select, output reg out); @@ -396,7 +396,7 @@ always @( in or select) 14: out = in[14]; 15: out = in[15]; endcase -endmodule +endmodule module MUX32(input [31:0] in, input [4:0] select, output reg out); @@ -435,7 +435,7 @@ always @( in or select) 30: out = in[30]; 31: out = in[31]; endcase -endmodule +endmodule module MUX64(input [63:0] in, input [5:0] select, output reg out); @@ -506,7 +506,7 @@ always @( in or select) 62: out = in[62]; 63: out = in[63]; endcase -endmodule +endmodule module ADD1(input in1, in2, cin, output out, cout); @@ -514,41 +514,41 @@ assign {cout, out} = in1 + in2 + cin; endmodule -module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; @@ -561,41 +561,41 @@ assign {cout, out} = in1 - in2 - cin; endmodule -module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; @@ -651,7 +651,7 @@ assign rem = in1%in2; endmodule -module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -659,7 +659,7 @@ assign rem = in1%in2; endmodule -module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -667,7 +667,7 @@ assign rem = in1%in2; endmodule -module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -675,7 +675,7 @@ assign rem = in1%in2; endmodule -module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -683,7 +683,7 @@ assign rem = in1%in2; endmodule -module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -691,7 +691,7 @@ assign rem = in1%in2; endmodule -module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -711,7 +711,7 @@ always @(posedge clk or posedge reset) q <= 0; else q <= d; -endmodule +endmodule module SFF(input d, clk, set, output reg q); always @(posedge clk or posedge set) @@ -719,7 +719,7 @@ always @(posedge clk or posedge set) q <= 1; else q <= d; -endmodule +endmodule module RSFF(input d, clk, set, reset, output reg q); always @(posedge clk or posedge reset or posedge set) @@ -745,30 +745,30 @@ module LATCH(input d, enable, output reg q); always @( d or enable) if(enable) q <= d; -endmodule +endmodule module RLATCH(input d, reset, enable, output reg q); always @( d or enable or reset) if(enable) if(reset) q <= 0; - else + else q <= d; -endmodule +endmodule module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); always @ (in, shift, val) begin if(shift) out = val; - else + else out = in; end endmodule -module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -776,58 +776,58 @@ always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); @@ -841,7 +841,7 @@ end endmodule -module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -849,12 +849,12 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); @@ -862,10 +862,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); @@ -873,11 +873,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); @@ -885,11 +885,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); @@ -897,10 +897,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); @@ -908,10 +908,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module CMP1 #(parameter SIZE = 1) (input in1, in2, +module CMP1 #(parameter SIZE = 1) (input in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -920,7 +920,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -928,17 +928,17 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, +module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -947,7 +947,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -955,16 +955,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, +module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -973,7 +973,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -981,16 +981,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, +module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -999,7 +999,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1007,16 +1007,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, +module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1025,7 +1025,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1033,16 +1033,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, +module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1051,7 +1051,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1059,16 +1059,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, +module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1077,7 +1077,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1085,12 +1085,12 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v index 54c07661..800cf822 100644 --- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex index 485b4f35..c2249d1f 100644 --- a/manual/CHAPTER_Verilog.tex +++ b/manual/CHAPTER_Verilog.tex @@ -550,23 +550,23 @@ process $proc$<input>:1$1 switch \in2 case 1'1 assign $1\out1[0:0] $logic_not$<input>:4$2_Y - case + case assign $1\out1[0:0] \in1 end switch \in3 case 1'1 assign $0\out2[0:0] \out2 - case + case end switch \in4 case 1'1 switch \in5 case 1'1 assign $0\out3[0:0] \in6 - case + case assign $0\out3[0:0] \in7 end - case + case end sync posedge \clock update \out1 $0\out1[0:0] diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 74350091..40b0802d 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -844,13 +844,13 @@ module adff2dff (CLK, ARST, D, Q); parameter CLK_POLARITY = 1; parameter ARST_POLARITY = 1; parameter ARST_VALUE = 0; - + input CLK, ARST; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; - + wire [1023:0] _TECHMAP_DO_ = "proc"; - + wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY; \end{lstlisting} \vss} diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v index b6d91b01..13ecf0ba 100644 --- a/manual/PRESENTATION_ExAdv/addshift_map.v +++ b/manual/PRESENTATION_ExAdv/addshift_map.v @@ -4,17 +4,17 @@ module \$add (A, B, Y); parameter A_WIDTH = 1; parameter B_WIDTH = 1; parameter Y_WIDTH = 1; - + input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - + parameter _TECHMAP_BITS_CONNMAP_ = 0; parameter _TECHMAP_CONNMAP_A_ = 0; parameter _TECHMAP_CONNMAP_B_ = 0; - + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH || _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_; - + assign Y = A << 1; endmodule diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/manual/PRESENTATION_ExAdv/red_or3x1_map.v index 24ca9dab..8c37b1db 100644 --- a/manual/PRESENTATION_ExAdv/red_or3x1_map.v +++ b/manual/PRESENTATION_ExAdv/red_or3x1_map.v @@ -3,10 +3,10 @@ module \$reduce_or (A, Y); parameter A_SIGNED = 0; parameter A_WIDTH = 0; parameter Y_WIDTH = 0; - + input [A_WIDTH-1:0] A; output [Y_WIDTH-1:0] Y; - + function integer min; input integer a, b; begin @@ -16,7 +16,7 @@ module \$reduce_or (A, Y); min = b; end endfunction - + genvar i; generate begin if (A_WIDTH == 0) begin diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v index 293c5b84..b4dbd9e0 100644 --- a/manual/PRESENTATION_ExAdv/sym_mul_map.v +++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v @@ -4,12 +4,12 @@ module \$mul (A, B, Y); parameter A_WIDTH = 1; parameter B_WIDTH = 1; parameter Y_WIDTH = 1; - + input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH; - + MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) ); endmodule diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex index f86dcd7a..6bc44c5c 100644 --- a/manual/PRESENTATION_ExOth.tex +++ b/manual/PRESENTATION_ExOth.tex @@ -33,7 +33,7 @@ as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design are connected. \item -Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used +Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used to transform the design into an equivialent design that is easier to analyse. \item @@ -115,7 +115,7 @@ The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking. \end{frame} \begin{frame}[t]{Example: Formal Equivalence Checking (1/2)} -Remember the following example? +Remember the following example? \vskip1em \vbox to 0cm{ diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index b7d6b8a6..1230f32a 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -22,7 +22,7 @@ \item Convert remaining logic to bit-level logic functions \item Perform optimizations on bit-level logic functions \item Map bit-level logic gates and registers to cell library -\item Write results to output file +\item Write results to output file \end{itemize} \end{frame} diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys index 8b3390ed..cc4e7cd3 100644 --- a/manual/PRESENTATION_Intro/counter.ys +++ b/manual/PRESENTATION_Intro/counter.ys @@ -1,4 +1,4 @@ -# read design +# read design read_verilog counter.v hierarchy -check -top counter diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 96189e55..97ec76fe 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -325,7 +325,7 @@ Simulation models (i.e. {\it documentation\/} :-) for the internal cell library: \bigskip The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable -width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}. +width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}. \bigskip The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index d653f409..9e542f77 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -2988,7 +2988,7 @@ from non-zero to zero in the test design. Write the current design to an SPICE netlist file. -big_endian - generate multi-bit ports in MSB first order + generate multi-bit ports in MSB first order (default is LSB first) -neg net_name diff --git a/misc/yosysjs/yosysjs.js b/misc/yosysjs/yosysjs.js index 65ed3049..9723386f 100644 --- a/misc/yosysjs/yosysjs.js +++ b/misc/yosysjs/yosysjs.js @@ -67,7 +67,7 @@ var YosysJS = new function() { if (reference_element) { if (reference_element.tagName == 'textarea') ys.init_script = reference_element.value; - + if (reference_element.tagName == 'iframe') { ys.iframe_element = reference_element; } else { diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 054cfc1c..e698926f 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -150,5 +150,5 @@ struct AddPass : public Pass { } } } AddPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index bb8fe78e..05781243 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -150,5 +150,5 @@ struct CheckPass : public Pass { log_error("Found %d problems in 'check -assert'.\n", counter); } } CheckPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index e17c1b1c..e09d636f 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -185,5 +185,5 @@ struct ConnectPass : public Pass { log_cmd_error("Expected -set, -unset, or -port.\n"); } } ConnectPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index a65a6364..1c66fb81 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -205,5 +205,5 @@ struct ConnwrappersPass : public Pass { worker.work(design, mod_it.second); } } ConnwrappersPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 459e5b0e..fb863512 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -55,5 +55,5 @@ struct CopyPass : public Pass { design->add(new_mod); } } CopyPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index b4362887..6d51d30e 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -140,5 +140,5 @@ struct DeletePass : public Pass { } } } DeletePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 9f800c31..16a4e64a 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 81e53259..6a002869 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -228,5 +228,5 @@ struct RenamePass : public Pass { } } } RenamePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 1cd55ecb..f083e1f6 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -69,5 +69,5 @@ struct ScatterPass : public Pass { } } } ScatterPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index f4eeac07..4acb5aef 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -340,5 +340,5 @@ struct SccPass : public Pass { } } } SccPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 9763ef60..6ceba296 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -564,7 +564,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se { if (design->selected_active_module.empty()) return; - + if (sel.full_selection) { sel.full_selection = false; sel.selected_modules.clear(); @@ -733,7 +733,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) select_filter_active_mod(design, work_stack.back()); return; } - + sel.full_selection = false; for (auto &mod_it : design->modules_) { @@ -1386,7 +1386,7 @@ struct SelectPass : public Pass { design->selection_stack.back().optimize(design); } } SelectPass; - + struct CdPass : public Pass { CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { } virtual void help() @@ -1458,7 +1458,7 @@ static void log_matches(const char *title, Module *module, T list) log(" %s\n", RTLIL::id2cstr(id)); } } - + struct LsPass : public Pass { LsPass() : Pass("ls", "list modules or objects in modules") { } virtual void help() @@ -1502,5 +1502,5 @@ struct LsPass : public Pass { } } } LsPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 58fcf028..75c738b6 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -127,7 +127,7 @@ struct SetattrPass : public Pass { } } } SetattrPass; - + struct SetparamPass : public Pass { SetparamPass() : Pass("setparam", "set/unset parameters on objects") { } virtual void help() @@ -175,7 +175,7 @@ struct SetparamPass : public Pass { } } } SetparamPass; - + struct ChparamPass : public Pass { ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { } virtual void help() @@ -251,5 +251,5 @@ struct ChparamPass : public Pass { } } } ChparamPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index b9a29b7d..9ca2e874 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -155,5 +155,5 @@ struct SetundefPass : public Pass { } } } SetundefPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0bcc7689..28e3decd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -845,5 +845,5 @@ struct ShowPass : public Pass { log_pop(); } } ShowPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 933b72c6..e56699f4 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -365,5 +365,5 @@ struct SplicePass : public Pass { } } } SplicePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index d22d6500..3cd857f4 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -198,5 +198,5 @@ struct SplitnetsPass : public Pass { } } } SplitnetsPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index bd3a43ac..0aa76467 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -239,5 +239,5 @@ struct StatPass : public Pass { log("\n"); } } StatPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index a6e2f01b..4ce750b1 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index a56730d4..a536fe30 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 5635e7a7..1cc4c3a7 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 23b34818..34318dec 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index b6e232f9..b5c383b6 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index f1b66432..1f52a632 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index 8ca1aacd..8a2f5e05 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index e76be40c..1ecf14a2 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -145,5 +145,5 @@ struct FsmPass : public Pass { log_pop(); } } FsmPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index c89553c6..7a621b56 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -191,5 +191,5 @@ struct FsmDetectPass : public Pass { muxtree_cells.clear(); } } FsmDetectPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index a261eb22..914dcf29 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -275,5 +275,5 @@ struct FsmExpandPass : public Pass { } } } FsmExpandPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index ad927033..0eff2884 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -3,11 +3,11 @@ * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index b5250970..7d68999f 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -241,7 +241,7 @@ static void extract_fsm(RTLIL::Wire *wire) { log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str()); - // get input and output signals for state ff + // get input and output signals for state ff RTLIL::SigSpec dff_out = assign_map(RTLIL::SigSpec(wire)); RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width); @@ -460,5 +460,5 @@ struct FsmExtractPass : public Pass { sig2trigger.clear(); } } FsmExtractPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 4a1f1d9a..20db82c1 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -58,5 +58,5 @@ struct FsmInfoPass : public Pass { } } } FsmInfoPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 155801a3..574b9a20 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -350,5 +350,5 @@ struct FsmMapPass : public Pass { } } } FsmMapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 4b93d79f..7322368c 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -75,14 +75,14 @@ struct FsmOpt fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state); } } - + bool signal_is_unused(RTLIL::SigSpec sig) { RTLIL::SigBit bit = sig.to_single_sigbit(); if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0) return false; - + char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str()); for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { if (tok[0] && bit.offset == atoi(tok)) { @@ -347,5 +347,5 @@ struct FsmOptPass : public Pass { } } } FsmOptPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 16996810..aa1e99be 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs fsm_data.state_bits = new_num_state_bits; } else log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); - + if (encfile) fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str()); @@ -134,7 +134,7 @@ struct FsmRecodePass : public Pass { log("\n"); log("This pass reassign the state encodings for FSM cells. At the moment only\n"); log("one-hot encoding and binary encoding is supported.\n"); - + log(" -encoding <type>\n"); log(" specify the encoding scheme used for FSMs without the\n"); log(" 'fsm_encoding' attribute or with the attribute set to `auto'.\n"); @@ -193,5 +193,5 @@ struct FsmRecodePass : public Pass { fclose(encfile); } } FsmRecodePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 5671d000..1b98ccba 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 57177032..d655af0d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 8d4012c5..be46d882 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -349,5 +349,5 @@ struct SubmodPass : public Pass { log_pop(); } } SubmodPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index 7623d872..4e74d1a4 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -89,5 +89,5 @@ struct MemoryPass : public Pass { log_pop(); } } MemoryPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 2e968b7a..7d98a7c4 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 7e088a1b..6bc4b44c 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -239,5 +239,5 @@ struct MemoryCollectPass : public Pass { handle_module(design, mod_it.second); } } MemoryCollectPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 0574dd40..5584f27c 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -256,5 +256,5 @@ struct MemoryDffPass : public Pass { } } } MemoryDffPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index bc94e1e2..524fa8d2 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -37,7 +37,7 @@ struct MemoryMapWorker { std::stringstream sstr; sstr << "$memory" << name.str() << token1; - + if (i >= 0) sstr << "[" << i << "]"; @@ -360,5 +360,5 @@ struct MemoryMapPass : public Pass { MemoryMapWorker(design, mod); } } MemoryMapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 1845d56e..b8f27025 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -79,7 +79,7 @@ struct MemoryShareWorker } return false; } - + for (int i = 0; i < int(sig_s.size()); i++) { diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 0f8d5217..c07c4b60 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -126,5 +126,5 @@ struct MemoryUnpackPass : public Pass { handle_module(design, mod_it.second); } } MemoryUnpackPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 6b075cd9..43defb78 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -4,8 +4,8 @@ OBJS += passes/opt/opt_share.o OBJS += passes/opt/opt_muxtree.o OBJS += passes/opt/opt_reduce.o OBJS += passes/opt/opt_rmdff.o -OBJS += passes/opt/opt_clean.o -OBJS += passes/opt/opt_const.o +OBJS += passes/opt/opt_clean.o +OBJS += passes/opt/opt_const.o ifneq ($(SMALL),1) OBJS += passes/opt/share.o diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 150cacf9..f5389d8e 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -162,5 +162,5 @@ struct OptPass : public Pass { log_pop(); } } OptPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index a34da781..16d6add8 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -159,7 +159,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos for (auto &it2 : cell->connections()) connected_signals.add(it2.second); } - + SigMap assign_map(module); pool<RTLIL::SigSpec> direct_sigs; pool<RTLIL::Wire*> direct_wires; @@ -368,7 +368,7 @@ struct OptCleanPass : public Pass { log_pop(); } } OptCleanPass; - + struct CleanPass : public Pass { CleanPass() : Pass("clean", "remove unused cells and wires") { } virtual void help() @@ -432,5 +432,5 @@ struct CleanPass : public Pass { ct_all.clear(); } } CleanPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a3980891..32a80426 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 98287074..15d59202 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -479,5 +479,5 @@ struct OptMuxtreePass : public Pass { log("Removed %d multiplexer ports.\n", total_count); } } OptMuxtreePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 5c36eb26..aec85b46 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -384,5 +384,5 @@ struct OptReducePass : public Pass { log("Performed a total of %d changes.\n", total_count); } } OptReducePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 84af6482..d2695b16 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -250,5 +250,5 @@ struct OptRmdffPass : public Pass { log("Replaced %d DFF cells.\n", total_count); } } OptRmdffPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 0e524e9e..39bc9821 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -335,5 +335,5 @@ struct OptSharePass : public Pass { log("Removed a total of %d cells.\n", total_count); } } OptSharePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/opt/share.cc b/passes/opt/share.cc index bf406bcd..b1b441da 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 72b4051f..70a40e96 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index 40b2b30f..577ff6bf 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -86,5 +86,5 @@ struct ProcPass : public Pass { log_pop(); } } ProcPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 1f08ab04..1da23728 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -288,5 +288,5 @@ struct ProcArstPass : public Pass { wire->attributes.erase("\\init"); } } ProcArstPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 82716cd0..35801951 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -183,5 +183,5 @@ struct ProcCleanPass : public Pass { log("Cleaned up %d empty switch%s.\n", total_count, total_count == 1 ? "" : "es"); } } ProcCleanPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 76842da6..63713139 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -382,5 +382,5 @@ struct ProcDffPass : public Pass { } } } ProcDffPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index e1bbab54..e37d81dd 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index dff68159..1d673805 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -111,5 +111,5 @@ struct ProcInitPass : public Pass { proc_init(mod, proc_it.second); } } ProcInitPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 4aa1aab5..904d9211 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -285,5 +285,5 @@ struct ProcMuxPass : public Pass { proc_mux(mod, proc_it.second); } } ProcMuxPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 427e0d56..f60d4b30 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -100,5 +100,5 @@ struct ProcRmdeadPass : public Pass { log("Removed a total of %d dead cases.\n", total_counter); } } ProcRmdeadPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 01d0e031..d97fa6f1 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -448,7 +448,7 @@ struct EvalPass : public Pass { RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first)); module = mod_it.second; } - if (module == NULL) + if (module == NULL) log_cmd_error("Can't perform EVAL on an empty selection!\n"); ConstEval ce(module); @@ -599,5 +599,5 @@ struct EvalPass : public Pass { } } } EvalPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index b012bc6a..3d2bcf63 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -646,5 +646,5 @@ struct ExposePass : public Pass { } } } ExposePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index a60de4ee..f9d3a82a 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -836,5 +836,5 @@ struct FreducePass : public Pass { log("Rewired a total of %d signal bits.\n", bitcount); } } FreducePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9853cd0c..7c48e5b9 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -61,7 +61,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: } if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-") that->cmd_error(args, argidx, "command argument error"); - + RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]); RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]); RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); @@ -301,5 +301,5 @@ struct MiterPass : public Pass { log_cmd_error("Missing mode parameter!\n"); } } MiterPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index a420011e..16ec88fe 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index a180e311..1449f2e8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -1537,5 +1537,5 @@ struct AbcPass : public Pass { log_pop(); } } AbcPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 5253b0f8..db1c731e 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -108,7 +108,7 @@ struct AigmapPass : public Pass { if (node.inverter) bit = module->NotGate(NEW_ID, bit); - + skip_inverter: for (auto &op : node.outports) module->connect(cell->getPort(op.first)[op.second], bit); @@ -145,5 +145,5 @@ struct AigmapPass : public Pass { } } } AigmapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index dcffed94..54c9bc1a 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -563,5 +563,5 @@ struct AlumaccPass : public Pass { } } } AlumaccPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 5ebc3ef9..e587f827 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -365,5 +365,5 @@ struct Dff2dffePass : public Pass { } } } Dff2dffePass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 3317e8af..2215c18e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -117,5 +117,5 @@ struct DffinitPass : public Pass { } } } DffinitPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 9f534c2e..64131c1a 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -80,7 +80,7 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, { if (cell == NULL || attr == NULL || attr->value.empty()) return false; - + std::string value = attr->value; for (size_t pos = value.find_first_of("\" \t()"); pos != std::string::npos; pos = value.find_first_of("\" \t()")) @@ -562,7 +562,7 @@ struct DfflibmapPass : public Pass { map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN1_"); map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP0_"); map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP1_"); - + log(" final dff cell mappings:\n"); logmap_all(); @@ -573,5 +573,5 @@ struct DfflibmapPass : public Pass { cell_mappings.clear(); } } DfflibmapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 27689663..b670083b 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -650,7 +650,7 @@ struct ExtractPass : public Pass { haystack_map[graph_name] = mod_it.second; } } - + if (!mine_mode) { std::vector<SubCircuit::Solver::Result> results; @@ -759,5 +759,5 @@ struct ExtractPass : public Pass { log_pop(); } } ExtractPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 9a14ffa3..a0bd2f9a 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -119,5 +119,5 @@ struct HilomapPass : public Pass { } } } HilomapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 3fba0e61..0e0a2adc 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -202,5 +202,5 @@ struct IopadmapPass : public Pass { } } } IopadmapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index def48039..d5254c02 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -173,7 +173,7 @@ LibertyAst *LibertyParser::parse() if (tok == '}' || tok < 0) return NULL; - + if (tok != 'v') error(); diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index e947bd8c..cf632557 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 8068cd9e..dad1c06a 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -400,5 +400,5 @@ struct MaccmapPass : public Pass { } } } MaccmapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 18d04204..b250c568 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -530,7 +530,7 @@ struct MuxcoverWorker int count_muxes_by_type[4] = {0, 0, 0, 0}; find_best_cover(tree, tree.root); implement_best_cover(tree, tree.root, count_muxes_by_type); - log(" Replaced tree at %s: %d MUX2, %d MUX4, %d MUX8, %d MUX16\n", log_signal(tree.root), + log(" Replaced tree at %s: %d MUX2, %d MUX4, %d MUX8, %d MUX16\n", log_signal(tree.root), count_muxes_by_type[0], count_muxes_by_type[1], count_muxes_by_type[2], count_muxes_by_type[3]); for (auto &it : tree.muxes) module->remove(it.second); @@ -628,5 +628,5 @@ struct MuxcoverPass : public Pass { } } } MuxcoverPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index 87762c0b..3c12bfd0 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -56,7 +56,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, SigSpec right_sel = sig_sel.extract(left_size, right_size); SigSpec left_or, left_result, right_result; - + left_result = recursive_mux_generator(module, left_data, left_sel, left_or); right_result = recursive_mux_generator(module, right_data, right_sel, sig_or); left_or = or_generator(module, left_or); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 6cd1c586..7511a55c 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -97,7 +97,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (sig_y.size() == 0) return; - + if (sig_a.size() == 0) { if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); @@ -197,7 +197,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) if (sig_y.size() == 0) return; - + if (sig_y.size() > 1) { module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); @@ -221,7 +221,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) if (sig_y.size() == 0) return; - + if (sig_y.size() > 1) { module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); @@ -549,5 +549,5 @@ struct SimplemapPass : public Pass { } } } SimplemapPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h index 67be4efe..c2d73ea7 100644 --- a/passes/techmap/simplemap.h +++ b/passes/techmap/simplemap.h @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c36eb2ed..63923a5c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -1088,7 +1088,7 @@ struct TechmapPass : public Pass { log_pop(); } } TechmapPass; - + struct FlattenPass : public Pass { FlattenPass() : Pass("flatten", "flatten design") { } virtual void help() diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 7c1b671c..5d573ad6 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -349,6 +349,6 @@ struct TestAutotbBackend : public Backend { autotest(*f, design, num_iter); } } TestAutotbBackend; - + PRIVATE_NAMESPACE_END diff --git a/techlibs/cmos/counter.v b/techlibs/cmos/counter.v index 68b5c05b..f2165872 100644 --- a/techlibs/cmos/counter.v +++ b/techlibs/cmos/counter.v @@ -2,7 +2,7 @@ module counter (clk, rst, en, count); input clk, rst, en; output reg [2:0] count; - + always @(posedge clk) if (rst) count <= 3'd0; diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index d85cf5ad..66970620 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f3a12717..ddc7fe3b 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index f6853651..4c819e23 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -211,5 +211,5 @@ struct SynthPass : public Pass { log_pop(); } } SynthPass; - + PRIVATE_NAMESPACE_END diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index f67e3658..e4974789 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -20,7 +20,7 @@ * The internal logic cell technology mapper. * * This verilog library contains the mapping of internal cells (e.g. $not with - * variable bit width) to the internal logic cells (such as the single bit $_NOT_ + * variable bit width) to the internal logic cells (such as the single bit $_NOT_ * gate). Usually this logic network is then mapped to the actual technology * using e.g. the "abc" pass. * diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index b0f66a2a..4449fdc1 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 47370117..afa8a516 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -15,7 +15,7 @@ module SB_IO ( ); parameter [5:0] PIN_TYPE = 6'b000000; parameter [0:0] PULLUP = 1'b0; - parameter [0:0] NEG_TRIGGER = 1'b0; + parameter [0:0] NEG_TRIGGER = 1'b0; parameter IO_STANDARD = "SB_LVCMOS"; reg dout, din_0, din_1; @@ -74,7 +74,7 @@ module SB_GB_IO ( ); parameter [5:0] PIN_TYPE = 6'b000000; parameter [0:0] PULLUP = 1'b0; - parameter [0:0] NEG_TRIGGER = 1'b0; + parameter [0:0] NEG_TRIGGER = 1'b0; parameter IO_STANDARD = "SB_LVCMOS"; assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN; diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index 4159d859..9ebc3c0d 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -119,5 +119,5 @@ struct Ice40FfssrPass : public Pass { } } } Ice40FfssrPass; - + PRIVATE_NAMESPACE_END diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 990d29aa..6acefaf4 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -166,5 +166,5 @@ struct Ice40OptPass : public Pass { log_pop(); } } Ice40OptPass; - + PRIVATE_NAMESPACE_END diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 236c27a5..4499263a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -272,5 +272,5 @@ struct SynthIce40Pass : public Pass { log_pop(); } } SynthIce40Pass; - + PRIVATE_NAMESPACE_END diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index a154f774..03719659 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt index 5e71c468..894e714c 100644 --- a/techlibs/xilinx/brams.txt +++ b/techlibs/xilinx/brams.txt @@ -102,4 +102,4 @@ match $__XILINX_RAMB18_TDP shuffle_enable B make_transp endmatch - + diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8ef0fae1..b3d4c214 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -231,5 +231,5 @@ struct SynthXilinxPass : public Pass { log_pop(); } } SynthXilinxPass; - + PRIVATE_NAMESPACE_END diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py index 352eedb0..fb5695ff 100644 --- a/tests/fsm/generate.py +++ b/tests/fsm/generate.py @@ -108,4 +108,4 @@ for idx in range(50): print('cd ..') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) - + diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py index 16f68f05..aee21118 100644 --- a/tests/realmath/generate.py +++ b/tests/realmath/generate.py @@ -39,7 +39,7 @@ def random_expression(depth = 3, maxparam = 0): return op + '(' + recursion() + ', ' + recursion() + ')' raise -for idx in range(100): +for idx in range(100): with open('temp/uut_%05d.v' % idx, 'w') as f: with redirect_stdout(f): print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) @@ -91,4 +91,4 @@ for idx in range(100): print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) print('end') print('endmodule') - + diff --git a/tests/share/generate.py b/tests/share/generate.py index 7f8a5951..271dd9c4 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -72,4 +72,4 @@ for idx in range(100): print('tee -a temp/all_share_log.txt share -aggressive gate') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') - + diff --git a/tests/simple/loops.v b/tests/simple/loops.v index 77cdcd8e..d7743a42 100644 --- a/tests/simple/loops.v +++ b/tests/simple/loops.v @@ -41,10 +41,10 @@ begin keysched_last_key_i = key_i; else keysched_last_key_i = keysched_new_key_o; - + if (round == 0 && addroundkey_start_i) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = key_i; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; @@ -66,7 +66,7 @@ begin end else if (addroundkey_round == round && keysched_ready_o) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = keysched_new_key_o; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index bed5528d..40f490b7 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -47,7 +47,7 @@ endmodule // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); -reg [7:0] dint_c [0:7]; +reg [7:0] dint_c [0:7]; always @(posedge clk) begin {dout_a[0], dint_c[3]} <= din_a; diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v index dc8860de..569a28ad 100644 --- a/tests/simple/omsp_dbg_uart.v +++ b/tests/simple/omsp_dbg_uart.v @@ -22,13 +22,13 @@ always @(uart_state or mem_burst) RX_DATA : uart_state_nxt = RX_SYNC; default : uart_state_nxt = RX_CMD; endcase - + always @(posedge dbg_clk or posedge dbg_rst) if (dbg_rst) uart_state <= RX_SYNC; else if (xfer_done | mem_burst) uart_state <= uart_state_nxt; assign cmd_valid = (uart_state==RX_CMD) & xfer_done; assign xfer_done = uart_state!=RX_SYNC; - + endmodule |