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-rw-r--r--passes/cmds/add.cc4
-rw-r--r--passes/cmds/connect.cc6
-rw-r--r--passes/cmds/connwrappers.cc2
-rw-r--r--passes/cmds/scatter.cc4
-rw-r--r--passes/cmds/scc.cc2
-rw-r--r--passes/cmds/select.cc4
-rw-r--r--passes/cmds/setundef.cc4
-rw-r--r--passes/cmds/show.cc16
-rw-r--r--passes/cmds/splice.cc18
-rw-r--r--passes/cmds/splitnets.cc2
10 files changed, 31 insertions, 31 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index ce8ecc32..1401193f 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
if (mod->get_bool_attribute("\\blackbox"))
continue;
- if (it.second->connections_.count(name) > 0)
+ if (it.second->connections().count(name) > 0)
continue;
- it.second->connections_[name] = wire;
+ it.second->set(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
}
}
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index ea05026f..99a28d4a 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -123,7 +123,7 @@ struct ConnectPass : public Pass {
SigMap sigmap;
if (!flag_nomap)
- for (auto &it : module->connections_) {
+ for (auto &it : module->connections()) {
std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
for (size_t i = 0; i < lhs.size(); i++)
@@ -148,7 +148,7 @@ struct ConnectPass : public Pass {
if (!flag_nounset)
unset_drivers(design, module, sigmap, sig_lhs);
- module->connections_.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
+ module->connect(RTLIL::SigSig(sig_lhs, sig_rhs));
}
else
if (!unset_expr.empty())
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
- module->cells.at(RTLIL::escape_id(port_cell))->connections_[RTLIL::escape_id(port_port)] = sigmap(sig);
+ module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
}
else
log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 87ed3d85..9faeffaf 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -74,7 +74,7 @@ struct ConnwrappersWorker
if (!decl_celltypes.count(cell->type))
continue;
- for (auto &conn : cell->connections_)
+ for (auto &conn : cell->connections())
{
std::pair<std::string, std::string> key(cell->type, conn.first);
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 0028f7ea..35ce0a11 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -58,10 +58,10 @@ struct ScatterPass : public Pass {
if (ct.cell_output(c.second->type, p.first)) {
RTLIL::SigSig sigsig(p.second, wire);
- mod_it.second->connections_.push_back(sigsig);
+ mod_it.second->connect(sigsig);
} else {
RTLIL::SigSig sigsig(wire, p.second);
- mod_it.second->connections_.push_back(sigsig);
+ mod_it.second->connect(sigsig);
}
p.second = wire;
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 40a2e48c..3380a935 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -132,7 +132,7 @@ struct SccWorker
RTLIL::SigSpec inputSignals, outputSignals;
- for (auto &conn : cell->connections_)
+ for (auto &conn : cell->connections())
{
bool isInput = true, isOutput = true;
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 5d991d03..e0f1a6d6 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
selected_wires.insert(it.second);
- for (auto &conn : mod->connections_)
+ for (auto &conn : mod->connections())
{
std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
}
for (auto &cell : mod->cells)
- for (auto &conn : cell.second->connections_)
+ for (auto &conn : cell.second->connections())
{
char last_mode = '-';
for (auto &rule : rules) {
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index e1005a27..e2610610 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -135,7 +135,7 @@ struct SetundefPass : public Pass {
CellTypes ct(design);
for (auto &it : module->cells)
- for (auto &conn : it.second->connections_)
+ for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
@@ -144,7 +144,7 @@ struct SetundefPass : public Pass {
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
- module->connections_.push_back(RTLIL::SigSig(c, bits));
+ module->connect(RTLIL::SigSig(c, bits));
}
}
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 29b83a9a..d63d9897 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -87,17 +87,17 @@ struct ShowWorker
return defaultColor;
}
- std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
+ std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
{
return nextColor(conn.first, nextColor(conn.second, defaultColor));
}
- std::string nextColor(RTLIL::SigSpec &sig)
+ std::string nextColor(const RTLIL::SigSpec &sig)
{
return nextColor(sig, nextColor());
}
- std::string nextColor(RTLIL::SigSig &conn)
+ std::string nextColor(const RTLIL::SigSig &conn)
{
return nextColor(conn, nextColor());
}
@@ -344,7 +344,7 @@ struct ShowWorker
std::vector<RTLIL::IdString> in_ports, out_ports;
- for (auto &conn : it.second->connections_) {
+ for (auto &conn : it.second->connections()) {
if (!ct.cell_output(it.second->type, conn.first))
in_ports.push_back(conn.first);
else
@@ -368,7 +368,7 @@ struct ShowWorker
label_string += "}}";
std::string code;
- for (auto &conn : it.second->connections_) {
+ for (auto &conn : it.second->connections()) {
code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
conn.second, ct.cell_output(it.second->type, conn.first));
}
@@ -421,7 +421,7 @@ struct ShowWorker
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
}
- for (auto &conn : module->connections_)
+ for (auto &conn : module->connections())
{
bool found_lhs_wire = false;
for (auto &c : conn.first.chunks()) {
@@ -516,7 +516,7 @@ struct ShowWorker
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
- if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) {
+ if (module->cells.empty() && module->connections().empty() && module->processes.empty()) {
log("Skipping empty module %s.\n", id2cstr(module->name));
continue;
} else
@@ -695,7 +695,7 @@ struct ShowPass : public Pass {
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
- if (mod_it.second->cells.empty() && mod_it.second->connections_.empty())
+ if (mod_it.second->cells.empty() && mod_it.second->connections().empty())
continue;
if (design->selected_module(mod_it.first))
modcount++;
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index c8b3d0b0..8b7e0406 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -74,9 +74,9 @@ struct SpliceWorker
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
- cell->connections_["\\A"] = sig_a;
- cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size());
- new_sig = cell->connections_["\\Y"];
+ cell->set("\\A", sig_a);
+ cell->set("\\Y", module->addWire(NEW_ID, sig.size()));
+ new_sig = cell->get("\\Y");
}
sliced_signals_cache[sig] = new_sig;
@@ -130,10 +130,10 @@ struct SpliceWorker
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
- cell->connections_["\\A"] = new_sig;
- cell->connections_["\\B"] = sig2;
- cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
- new_sig = cell->connections_["\\Y"];
+ cell->set("\\A", new_sig);
+ cell->set("\\B", sig2);
+ cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
+ new_sig = cell->get("\\Y");
}
spliced_signals_cache[sig] = new_sig;
@@ -159,7 +159,7 @@ struct SpliceWorker
}
for (auto &it : module->cells)
- for (auto &conn : it.second->connections_)
+ for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second);
driven_chunks.insert(sig);
@@ -232,7 +232,7 @@ struct SpliceWorker
it.first->port_output = false;
module->add(it.first);
module->add(new_port);
- module->connections_.push_back(RTLIL::SigSig(new_port, it.second));
+ module->connect(RTLIL::SigSig(new_port, it.second));
}
}
};
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 497d0a2a..28575e7b 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -134,7 +134,7 @@ struct SplitnetsPass : public Pass {
std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
for (auto &c : module->cells)
- for (auto &p : c.second->connections_)
+ for (auto &p : c.second->connections())
{
if (!ct.cell_known(c.second->type))
continue;
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 14:38:47 +0000