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-rw-r--r--techlibs/common/simlib.v14
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 275c469b..2a56b3a1 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1156,6 +1156,20 @@ endmodule
`endif
// --------------------------------------------------------
+module \$tribuf (A, EN, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input EN;
+output [WIDTH-1:0] Y;
+
+assign Y = EN ? A : 'bz;
+
+endmodule
+
+// --------------------------------------------------------
+
module \$assert (A, EN);
input A, EN;