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-rw-r--r--techlibs/common/Makefile.inc3
-rw-r--r--techlibs/common/cmp2lut.v105
-rw-r--r--techlibs/common/gate2lut.v87
-rw-r--r--techlibs/common/prep.cc8
-rw-r--r--techlibs/common/simcells.v4
-rw-r--r--techlibs/common/simlib.v176
-rw-r--r--techlibs/common/synth.cc50
7 files changed, 420 insertions, 13 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index ab961ac0..0e05620b 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -25,5 +25,6 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
+$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
+$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
-
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
new file mode 100644
index 00000000..8aa1eb95
--- /dev/null
+++ b/techlibs/common/cmp2lut.v
@@ -0,0 +1,105 @@
+// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
+// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
+// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
+// cannot be optimized further.
+//
+// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
+// with n <= k inputs should be techmapped in this way, because this shortens the critical path
+// from n to 1 by avoiding carry chains.
+
+(* techmap_celltype = "$eq $ne $lt $le $gt $ge" *)
+module _90_lut_cmp_ (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+parameter _TECHMAP_CELLTYPE_ = "";
+
+parameter _TECHMAP_CONSTMSK_A_ = 0;
+parameter _TECHMAP_CONSTVAL_A_ = 0;
+parameter _TECHMAP_CONSTMSK_B_ = 0;
+parameter _TECHMAP_CONSTVAL_B_ = 0;
+
+function automatic integer gen_lut;
+ input integer width;
+ input integer operation;
+ input integer swap;
+ input integer sign;
+ input integer operand;
+ integer n, i_var, i_cst, lhs, rhs, o_bit;
+ begin
+ gen_lut = width'b0;
+ for (n = 0; n < (1 << width); n++) begin
+ if (sign)
+ i_var = n[width-1:0];
+ else
+ i_var = n;
+ i_cst = operand;
+ if (swap) begin
+ lhs = i_cst;
+ rhs = i_var;
+ end else begin
+ lhs = i_var;
+ rhs = i_cst;
+ end
+ if (operation == 0)
+ o_bit = (lhs < rhs);
+ if (operation == 1)
+ o_bit = (lhs <= rhs);
+ if (operation == 2)
+ o_bit = (lhs > rhs);
+ if (operation == 3)
+ o_bit = (lhs >= rhs);
+ if (operation == 4)
+ o_bit = (lhs == rhs);
+ if (operation == 5)
+ o_bit = (lhs != rhs);
+ gen_lut = gen_lut | (o_bit << n);
+ end
+ end
+endfunction
+
+generate
+ if (_TECHMAP_CELLTYPE_ == "$lt")
+ localparam operation = 0;
+ if (_TECHMAP_CELLTYPE_ == "$le")
+ localparam operation = 1;
+ if (_TECHMAP_CELLTYPE_ == "$gt")
+ localparam operation = 2;
+ if (_TECHMAP_CELLTYPE_ == "$ge")
+ localparam operation = 3;
+ if (_TECHMAP_CELLTYPE_ == "$eq")
+ localparam operation = 4;
+ if (_TECHMAP_CELLTYPE_ == "$ne")
+ localparam operation = 5;
+
+ if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
+ wire _TECHMAP_FAIL_ = 1;
+ else if (&_TECHMAP_CONSTMSK_B_)
+ \$lut #(
+ .WIDTH(A_WIDTH),
+ .LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .Y(Y)
+ );
+ else if (&_TECHMAP_CONSTMSK_A_)
+ \$lut #(
+ .WIDTH(B_WIDTH),
+ .LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
+ ) _TECHMAP_REPLACE_ (
+ .A(B),
+ .Y(Y)
+ );
+ else
+ wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
new file mode 100644
index 00000000..99c123f4
--- /dev/null
+++ b/techlibs/common/gate2lut.v
@@ -0,0 +1,87 @@
+(* techmap_celltype = "$_NOT_" *)
+module _90_lut_not (A, Y);
+ input A;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b01)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_OR_" *)
+module _90_lut_or (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b1110)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_AND_" *)
+module _90_lut_and (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b1000)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_XOR_" *)
+module _90_lut_xor (A, B, Y);
+ input A, B;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ .LUT(4'b0110)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$_MUX_" *)
+module _90_lut_mux (A, B, S, Y);
+ input A, B, S;
+ output Y;
+
+ wire [`LUT_WIDTH-1:0] AA;
+ assign AA = {S, B, A};
+
+ \$lut #(
+ .WIDTH(`LUT_WIDTH),
+ // A 1010 1010
+ // B 1100 1100
+ // S 1111 0000
+ .LUT(8'b_1100_1010)
+ ) lut (
+ .A(AA),
+ .Y(Y)
+ );
+endmodule
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 897f37db..cdd21c3b 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -153,7 +153,7 @@ struct PrepPass : public ScriptPass
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing PREP pass.\n");
log_push();
@@ -195,9 +195,11 @@ struct PrepPass : public ScriptPass
run(nokeepdc ? "opt" : "opt -keepdc");
if (!ifxmode) {
if (help_mode)
- run("wreduce [-memx]");
- else
+ run("wreduce -keepdc [-memx]");
+ else if (nokeepdc)
run(memxmode ? "wreduce -memx" : "wreduce");
+ else
+ run(memxmode ? "wreduce -keepdc -memx" : "wreduce -keepdc");
}
if (!nomemmode) {
run(string("memory_dff") + (help_mode ? " [-nordff]" : nordff ? " -nordff" : ""));
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 937512e7..289673e8 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -465,7 +465,7 @@ endmodule
//-
//- $_SR_NP_ (S, R, Q)
//-
-//- A set-reset latch with negative polarity SET and positive polarioty RESET.
+//- A set-reset latch with negative polarity SET and positive polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
@@ -489,7 +489,7 @@ endmodule
//-
//- $_SR_PN_ (S, R, Q)
//-
-//- A set-reset latch with positive polarity SET and negative polarioty RESET.
+//- A set-reset latch with positive polarity SET and negative polarity RESET.
//-
//- Truth table: S R | Q
//- -----+---
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe05..a424d308 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1271,6 +1271,181 @@ endmodule
// --------------------------------------------------------
+module \$specify2 (EN, SRC, DST);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ if (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specify3 (EN, SRC, DST, DAT);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter EDGE_EN = 0;
+parameter EDGE_POL = 0;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter DAT_DST_PEN = 0;
+parameter DAT_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST, DAT;
+
+localparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ // DD=0
+
+ if (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ // DD=1
+
+ if (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ // DD=2
+
+ if (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specrule (EN_SRC, EN_DST, SRC, DST);
+
+parameter TYPE = "";
+parameter T_LIMIT = 0;
+parameter T_LIMIT2 = 0;
+
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_PEN = 0;
+parameter SRC_POL = 0;
+
+parameter DST_PEN = 0;
+parameter DST_POL = 0;
+
+input EN_SRC, EN_DST;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ // TBD
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
module \$assert (A, EN);
input A, EN;
@@ -1863,4 +2038,5 @@ end
endmodule
`endif
+
// --------------------------------------------------------
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index efb21475..e41c0fe9 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -51,6 +51,9 @@ struct SynthPass : public ScriptPass
log(" -encfile <file>\n");
log(" passed to 'fsm_recode' via 'fsm'\n");
log("\n");
+ log(" -lut <k>\n");
+ log(" perform synthesis for a k-LUT architecture.\n");
+ log("\n");
log(" -nofsm\n");
log(" do not run FSM optimization\n");
log("\n");
@@ -80,6 +83,7 @@ struct SynthPass : public ScriptPass
string top_module, fsm_opts, memory_opts;
bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
+ int lut;
void clear_flags() YS_OVERRIDE
{
@@ -89,6 +93,7 @@ struct SynthPass : public ScriptPass
autotop = false;
flatten = false;
+ lut = 0;
noalumacc = false;
nofsm = false;
noabc = false;
@@ -130,6 +135,10 @@ struct SynthPass : public ScriptPass
flatten = true;
continue;
}
+ if (args[argidx] == "-lut") {
+ lut = atoi(args[++argidx].c_str());
+ continue;
+ }
if (args[argidx] == "-nofsm") {
nofsm = true;
continue;
@@ -155,7 +164,7 @@ struct SynthPass : public ScriptPass
extra_args(args, argidx, design);
if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
+ log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();
@@ -186,19 +195,25 @@ struct SynthPass : public ScriptPass
{
run("proc");
if (help_mode || flatten)
- run("flatten", "(if -flatten)");
+ run("flatten", " (if -flatten)");
run("opt_expr");
run("opt_clean");
run("check");
run("opt");
run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ if (help_mode)
+ run("techmap -map +/cmp2lut.v", " (if -lut)");
+ else
+ run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut));
if (!noalumacc)
- run("alumacc");
+ run("alumacc", " (unless -noalumacc)");
if (!noshare)
- run("share");
+ run("share", " (unless -noshare)");
run("opt");
if (!nofsm)
- run("fsm" + fsm_opts);
+ run("fsm" + fsm_opts, " (unless -nofsm)");
run("opt -fast");
run("memory -nomap" + memory_opts);
run("opt_clean");
@@ -210,12 +225,33 @@ struct SynthPass : public ScriptPass
run("memory_map");
run("opt -full");
run("techmap");
+ if (help_mode)
+ {
+ run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
+ run("clean; opt_lut", " (if -noabc and -lut)");
+ }
+ else if (noabc && lut)
+ {
+ run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
+ run("clean; opt_lut");
+ }
run("opt -fast");
if (!noabc) {
#ifdef YOSYS_ENABLE_ABC
- run("abc -fast");
- run("opt -fast");
+ if (help_mode)
+ {
+ run("abc -fast", " (unless -noabc, unless -lut)");
+ run("abc -fast -lut k", "(unless -noabc, if -lut)");
+ }
+ else
+ {
+ if (lut)
+ run(stringf("abc -fast -lut %d", lut));
+ else
+ run("abc -fast");
+ }
+ run("opt -fast", " (unless -noabc)");
#endif
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 15:17:36 +0000