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Diffstat (limited to 'techlibs/xilinx/tests/bram1.v')
-rw-r--r--techlibs/xilinx/tests/bram1.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/bram1.v b/techlibs/xilinx/tests/bram1.v
index 034cc18e..ac7140a0 100644
--- a/techlibs/xilinx/tests/bram1.v
+++ b/techlibs/xilinx/tests/bram1.v
@@ -10,10 +10,27 @@ module bram1 #(
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
+ localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
+ localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
+ localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
+ localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
+
+ localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
+ localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
+ localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
+ localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
+
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
+ initial begin
+ memory[INIT_ADDR_0] <= INIT_DATA_0;
+ memory[INIT_ADDR_1] <= INIT_DATA_1;
+ memory[INIT_ADDR_2] <= INIT_DATA_2;
+ memory[INIT_ADDR_3] <= INIT_DATA_3;
+ end
+
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;