summaryrefslogtreecommitdiff
path: root/techlibs/xilinx/tests
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/xilinx/tests')
-rw-r--r--techlibs/xilinx/tests/bram1.v17
-rw-r--r--techlibs/xilinx/tests/bram1_tb.v52
-rw-r--r--techlibs/xilinx/tests/bram2.sh2
-rw-r--r--techlibs/xilinx/tests/bram2.v19
-rw-r--r--techlibs/xilinx/tests/bram2_tb.v19
5 files changed, 90 insertions, 19 deletions
diff --git a/techlibs/xilinx/tests/bram1.v b/techlibs/xilinx/tests/bram1.v
index 034cc18e..ac7140a0 100644
--- a/techlibs/xilinx/tests/bram1.v
+++ b/techlibs/xilinx/tests/bram1.v
@@ -10,10 +10,27 @@ module bram1 #(
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
+ localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
+ localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
+ localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
+ localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
+
+ localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
+ localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
+ localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
+ localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
+
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [ABITS-1:0] RD_ADDR_BUF;
reg [DBITS-1:0] RD_DATA_BUF;
+ initial begin
+ memory[INIT_ADDR_0] <= INIT_DATA_0;
+ memory[INIT_ADDR_1] <= INIT_DATA_1;
+ memory[INIT_ADDR_2] <= INIT_DATA_2;
+ memory[INIT_ADDR_3] <= INIT_DATA_3;
+ end
+
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_ADDR_BUF <= RD_ADDR;
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index 8f854b74..e75dfe31 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -8,6 +8,16 @@ module bram1_tb #(
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
+ localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
+ localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
+ localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
+ localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
+
+ localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
+ localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
+ localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
+ localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
+
bram1 #(
// .ABITS(ABITS),
// .DBITS(DBITS),
@@ -68,6 +78,11 @@ module bram1_tb #(
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
+ memory[INIT_ADDR_0] = INIT_DATA_0;
+ memory[INIT_ADDR_1] = INIT_DATA_1;
+ memory[INIT_ADDR_2] = INIT_DATA_2;
+ memory[INIT_ADDR_3] = INIT_DATA_3;
+
xorshift64_next;
xorshift64_next;
xorshift64_next;
@@ -84,16 +99,33 @@ module bram1_tb #(
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
- if (DBITS > 64)
- WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
- else
- WR_DATA <= xorshift64_state;
- xorshift64_next;
- WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
- xorshift64_next;
- RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
- WR_EN <= xorshift64_state[55];
- xorshift64_next;
+ if (i == 0) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_0;
+ end else
+ if (i == 1) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_1;
+ end else
+ if (i == 2) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_2;
+ end else
+ if (i == 3) begin
+ WR_EN <= 0;
+ RD_ADDR <= INIT_ADDR_3;
+ end else begin
+ if (DBITS > 64)
+ WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
+ else
+ WR_DATA <= xorshift64_state;
+ xorshift64_next;
+ WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
+ xorshift64_next;
+ RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
+ WR_EN <= xorshift64_state[55];
+ xorshift64_next;
+ end
#1; clk <= 1;
#1; clk <= 0;
diff --git a/techlibs/xilinx/tests/bram2.sh b/techlibs/xilinx/tests/bram2.sh
index d8d8ed30..5d9c84da 100644
--- a/techlibs/xilinx/tests/bram2.sh
+++ b/techlibs/xilinx/tests/bram2.sh
@@ -3,6 +3,6 @@
set -ex
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
-iverilog -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
+iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
vvp -N bram2_tb
diff --git a/techlibs/xilinx/tests/bram2.v b/techlibs/xilinx/tests/bram2.v
index 9444fb17..0a6013ca 100644
--- a/techlibs/xilinx/tests/bram2.v
+++ b/techlibs/xilinx/tests/bram2.v
@@ -1,18 +1,29 @@
module myram(
input rd_clk,
input [ 7:0] rd_addr,
- output reg [15:0] rd_data,
+ output reg [17:0] rd_data,
input wr_clk,
input wr_enable,
input [ 7:0] wr_addr,
- input [15:0] wr_data
+ input [17:0] wr_data
);
- reg [15:0] memory [0:255];
+ reg [17:0] memory [0:255];
integer i;
+ function [17:0] hash(input [7:0] k);
+ reg [31:0] x;
+ begin
+ x = {k, ~k, k, ~k};
+ x = x ^ (x << 13);
+ x = x ^ (x >> 17);
+ x = x ^ (x << 5);
+ hash = x;
+ end
+ endfunction
+
initial begin
for (i = 0; i < 256; i = i+1)
- memory[i] = i;
+ memory[i] = hash(i);
end
always @(posedge rd_clk)
diff --git a/techlibs/xilinx/tests/bram2_tb.v b/techlibs/xilinx/tests/bram2_tb.v
index 3a43b655..0fe4137c 100644
--- a/techlibs/xilinx/tests/bram2_tb.v
+++ b/techlibs/xilinx/tests/bram2_tb.v
@@ -3,12 +3,23 @@
module testbench;
reg rd_clk;
reg [ 7:0] rd_addr;
- wire [15:0] rd_data;
+ wire [17:0] rd_data;
wire wr_clk = 0;
wire wr_enable = 0;
wire [ 7:0] wr_addr = 0;
- wire [15:0] wr_data = 0;
+ wire [17:0] wr_data = 0;
+
+ function [17:0] hash(input [7:0] k);
+ reg [31:0] x;
+ begin
+ x = {k, ~k, k, ~k};
+ x = x ^ (x << 13);
+ x = x ^ (x >> 17);
+ x = x ^ (x << 5);
+ hash = x;
+ end
+ endfunction
myram uut (
.rd_clk (rd_clk ),
@@ -34,8 +45,8 @@ module testbench;
rd_addr <= rd_addr + 1;
@(posedge rd_clk);
// $display("%3d %3d", i, rd_data);
- if (i != rd_data) begin
- $display("[%1t] ERROR: addr=%3d, data=%3d", $time, i, rd_data);
+ if (hash(i) !== rd_data) begin
+ $display("[%1t] ERROR: addr=%3d, data_mem=%18b, data_ref=%18b", $time, i, rd_data, hash(i));
$stop;
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-31 14:04:08 +0000