diff options
Diffstat (limited to 'tests/simple')
45 files changed, 2702 insertions, 0 deletions
diff --git a/tests/simple/.gitignore b/tests/simple/.gitignore new file mode 100644 index 00000000..073f4615 --- /dev/null +++ b/tests/simple/.gitignore @@ -0,0 +1,2 @@ +*.log +*.out diff --git a/tests/simple/aes_kexp128.v b/tests/simple/aes_kexp128.v new file mode 100644 index 00000000..3ee03478 --- /dev/null +++ b/tests/simple/aes_kexp128.v @@ -0,0 +1,24 @@ + +// test taken from aes_core from iwls2005 + +module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3); + +input clk, kld; +input [15:0] key; +output [3:0] wo_0, wo_1, wo_2, wo_3; +reg [3:0] w[3:0]; + +assign wo_0 = w[0]; +assign wo_1 = w[1]; +assign wo_2 = w[2]; +assign wo_3 = w[3]; + +always @(posedge clk) begin + w[0] <= kld ? key[15:12] : w[0]; + w[1] <= kld ? key[11: 8] : w[0]^w[1]; + w[2] <= kld ? key[ 7: 4] : w[0]^w[1]^w[2]; + w[3] <= kld ? key[ 3: 0] : w[0]^w[1]^w[2]^w[3]; +end + +endmodule + diff --git a/tests/simple/always01.v b/tests/simple/always01.v new file mode 100644 index 00000000..21379cb0 --- /dev/null +++ b/tests/simple/always01.v @@ -0,0 +1,10 @@ +module uut_always01(clock, reset, count); + +input clock, reset; +output [3:0] count; +reg [3:0] count; + +always @(posedge clock) + count <= reset ? 0 : count + 1; + +endmodule diff --git a/tests/simple/always02.v b/tests/simple/always02.v new file mode 100644 index 00000000..8c7ef0fb --- /dev/null +++ b/tests/simple/always02.v @@ -0,0 +1,13 @@ +module uut_always02(clock, reset, count); + +input clock, reset; +output [3:0] count; +reg [3:0] count; + +always @(posedge clock) begin + count <= count + 1; + if (reset) + count <= 0; +end + +endmodule diff --git a/tests/simple/always03.v b/tests/simple/always03.v new file mode 100644 index 00000000..5542175e --- /dev/null +++ b/tests/simple/always03.v @@ -0,0 +1,22 @@ +module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3); + +input clock, in1, in2, in3, in4, in5, in6, in7; +output out1, out2, out3; +reg out1, out2, out3; + +always @(posedge clock) begin + out1 = in1; + if (in2) + out1 = !out1; + out2 <= out1; + if (in3) + out2 <= out2; + if (in4) + if (in5) + out3 <= in6; + else + out3 <= in7; + out1 = out1 ^ out2; +end + +endmodule diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v new file mode 100644 index 00000000..704ca3fd --- /dev/null +++ b/tests/simple/arraycells.v @@ -0,0 +1,15 @@ + +module array_test001(a, b, c, y); + input a; + input [31:0] b, c; + input [31:0] y; + + aoi12 p [31:0] (a, b, c, y); +endmodule + +module aoi12(a, b, c, y); + input a, b, c; + output y; + assign y = ~((a & b) | c); +endmodule + diff --git a/tests/simple/arrays01.v b/tests/simple/arrays01.v new file mode 100644 index 00000000..bd0eda29 --- /dev/null +++ b/tests/simple/arrays01.v @@ -0,0 +1,16 @@ +module uut_arrays01(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [15:0]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule diff --git a/tests/simple/carryadd.v b/tests/simple/carryadd.v new file mode 100644 index 00000000..4f777f79 --- /dev/null +++ b/tests/simple/carryadd.v @@ -0,0 +1,24 @@ +module carryadd(a, b, y); + +parameter WIDTH = 8; + +input [WIDTH-1:0] a, b; +output [WIDTH-1:0] y; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i+1) begin:STAGE + wire IN1 = a[i], IN2 = b[i]; + wire C, Y; + if (i == 0) + assign C = IN1 & IN2, Y = IN1 ^ IN2; + else + assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C), + Y = IN1 ^ IN2 ^ STAGE[i-1].C; + assign y[i] = Y; + end +endgenerate + +// assert property (y == a + b); + +endmodule diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v new file mode 100644 index 00000000..d1d8be86 --- /dev/null +++ b/tests/simple/constmuldivmod.v @@ -0,0 +1,27 @@ +module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); + always @* begin + case (mode) + 0: Y = A / 8'd0; + 1: Y = A % 8'd0; + 2: Y = A * 8'd0; + + 3: Y = A / 8'd1; + 4: Y = A % 8'd1; + 5: Y = A * 8'd1; + + 6: Y = A / 8'd2; + 7: Y = A % 8'd2; + 8: Y = A * 8'd2; + + 9: Y = A / 8'd4; + 10: Y = A % 8'd4; + 11: Y = A * 8'd4; + + 12: Y = A / 8'd8; + 13: Y = A % 8'd8; + 14: Y = A * 8'd8; + + default: Y = 8'd16 * A; + endcase + end +endmodule diff --git a/tests/simple/constpower.v b/tests/simple/constpower.v new file mode 100644 index 00000000..451866a6 --- /dev/null +++ b/tests/simple/constpower.v @@ -0,0 +1,15 @@ +module constpower(ys, yu); + +output [8*8*8-1:0] ys, yu; + +genvar i, j; + +generate + for (i = 0; i < 8; i = i+1) + for (j = 0; j < 8; j = j+1) begin:V + assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4); + assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j); + end +endgenerate + +endmodule diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v new file mode 100644 index 00000000..7765d6e2 --- /dev/null +++ b/tests/simple/dff_different_styles.v @@ -0,0 +1,105 @@ + +module dff(clk, d, q); +input clk, d; +output reg q; +always @(posedge clk) + q <= d; +endmodule + +module dffa(clk, arst, d, q); +input clk, arst, d; +output reg q; +always @(posedge clk or posedge arst) begin + if (arst) + q <= 1; + else + q <= d; +end +endmodule + +module dffa1(clk, arst, d, q); +input clk, arst, d; +output reg q; +always @(posedge clk or negedge arst) begin + if (~arst) + q <= 0; + else + q <= d; +end +endmodule + +module dffa2(clk, arst, d, q); +input clk, arst, d; +output reg q; +always @(posedge clk or negedge arst) begin + if (!arst) + q <= 0; + else + q <= d; +end +endmodule + +module dffa3(clk, arst, d, q); +input clk, arst, d; +output reg q; +always @(posedge clk or negedge arst) begin + if (~(!arst)) + q <= d; + else + q <= 1; +end +endmodule + +module dffa4(clk, arst1, arst2, arst3, d, q); +input clk, arst1, arst2, arst3, d; +output reg q; +always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin + if (arst1) + q <= 0; + else if (arst2) + q <= 0; + else if (!arst3) + q <= 0; + else + q <= d; +end +endmodule + +// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of +// simulation-implementation mismatches. The following testcases try to cover the +// part that is defined and avoid the undefined cases. + +module dffsr1(clk, arst, d, q); +input clk, arst, d; +output reg q; +always @(posedge clk, posedge arst) begin + if (arst) + q <= d^d; // constant expression -- but the frontend optimizer does not know that.. + else + q <= d; +end +endmodule + +module dffsr2(clk, preset, clear, d, q); +input clk, preset, clear, d; +output q; +(* gentb_clock *) +wire clk, preset, clear, d; +dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q); +endmodule + +(* gentb_skip *) +module dffsr2_sub(clk, preset, clear, d, q); +input clk, preset, clear, d; +output reg q; +always @(posedge clk, posedge preset, posedge clear) begin + if (preset) + q <= 1; + else if (clear) + q <= 0; + else + q <= d; +end +endmodule + + diff --git a/tests/simple/fiedler-cooley.v b/tests/simple/fiedler-cooley.v new file mode 100644 index 00000000..96861973 --- /dev/null +++ b/tests/simple/fiedler-cooley.v @@ -0,0 +1,33 @@ +// borrowed with some modifications from +// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html +module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out); + +input [8:0] data_in; +input clock, up, down; + +output reg [8:0] count_out; +output reg carry_out, borrow_out, parity_out; + +reg [9:0] cnt_up, cnt_dn; +reg [8:0] count_nxt; + +always @(posedge clock) +begin + cnt_dn = count_out - 3'b 101; + cnt_up = count_out + 2'b 11; + + case ({up,down}) + 2'b 00 : count_nxt = data_in; + 2'b 01 : count_nxt = cnt_dn; + 2'b 10 : count_nxt = cnt_up; + 2'b 11 : count_nxt = count_out; + default : count_nxt = 9'bX; + endcase + + parity_out <= ^count_nxt; + carry_out <= up & cnt_up[9]; + borrow_out <= down & cnt_dn[9]; + count_out <= count_nxt; +end + +endmodule diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v new file mode 100644 index 00000000..8b7aa279 --- /dev/null +++ b/tests/simple/forgen01.v @@ -0,0 +1,23 @@ + +// VERIFIC-SKIP + +module uut_forgen01(a, y); + +input [4:0] a; +output y; + +integer i, j; +reg [31:0] lut; + +initial begin + for (i = 0; i < 32; i = i+1) begin + lut[i] = i > 1; + for (j = 2; j*j <= i; j = j+1) + if (i % j == 0) + lut[i] = 0; + end +end + +assign y = lut[a]; + +endmodule diff --git a/tests/simple/forgen02.v b/tests/simple/forgen02.v new file mode 100644 index 00000000..14af070c --- /dev/null +++ b/tests/simple/forgen02.v @@ -0,0 +1,30 @@ +module uut_forgen02(a, b, cin, y, cout); + +parameter WIDTH = 8; + +input [WIDTH-1:0] a, b; +input cin; + +output [WIDTH-1:0] y; +output cout; + +genvar i; +wire [WIDTH-1:0] carry; + +generate + for (i = 0; i < WIDTH; i=i+1) begin:adder + wire [2:0] D; + assign D[1:0] = { a[i], b[i] }; + if (i == 0) begin:chain + assign D[2] = cin; + end else begin:chain + assign D[2] = carry[i-1]; + end + assign y[i] = ^D; + assign carry[i] = &D[1:0] | (^D[1:0] & D[2]); + end +endgenerate + +assign cout = carry[WIDTH-1]; + +endmodule diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v new file mode 100644 index 00000000..2dba14bb --- /dev/null +++ b/tests/simple/fsm.v @@ -0,0 +1,69 @@ + +// `define ASYNC_RESET + +module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b); + +input clk, reset, button_a, button_b; +output reg red_a, green_a, red_b, green_b; + +(* gentb_constant = 0 *) +wire reset; + +integer state; +reg [3:0] cnt; + +`ifdef ASYNC_RESET +always @(posedge clk, posedge reset) +`else +always @(posedge clk) +`endif +begin + cnt <= 0; + red_a <= 1; + red_b <= 1; + green_a <= 0; + green_b <= 0; + + if (reset) + state <= 100; + else + case (state) + 100: begin + if (button_a && !button_b) + state <= 200; + if (!button_a && button_b) + state <= 300; + end + 200: begin + red_a <= 0; + green_a <= 1; + cnt <= cnt + 1; + if (cnt == 5) + state <= 210; + end + 210: begin + red_a <= 0; + green_a <= cnt[0]; + cnt <= cnt + 1; + if (cnt == 10) + state <= 100; + end + 300: begin + red_b <= 0; + green_b <= 1; + cnt <= cnt + 1; + if (cnt == 5) + state <= 310; + end + 310: begin + red_b <= 0; + green_b <= cnt[0]; + cnt <= cnt + 1; + if (cnt == 10) + state <= 100; + end + endcase +end + +endmodule + diff --git a/tests/simple/generate.v b/tests/simple/generate.v new file mode 100644 index 00000000..24eb4462 --- /dev/null +++ b/tests/simple/generate.v @@ -0,0 +1,94 @@ + +module gen_test1(clk, a, b, y); + +input clk; +input [7:0] a, b; +output reg [7:0] y; + +genvar i, j; +wire [15:0] tmp1; + +generate + + for (i = 0; i < 8; i = i + 1) begin:gen1 + wire and_wire, or_wire; + assign and_wire = a[i] & b[i]; + assign or_wire = a[i] | b[i]; + if (i % 2 == 0) begin:gen2true + assign tmp1[i] = and_wire; + assign tmp1[i+8] = or_wire; + end else begin:gen2false + assign tmp1[i] = or_wire; + assign tmp1[i+8] = and_wire; + end + end + + for (i = 0; i < 8; i = i + 1) begin:gen3 + wire [4:0] tmp2; + for (j = 0; j <= 4; j = j + 1) begin:gen4 + wire tmpbuf; + assign tmpbuf = tmp1[i+2*j]; + assign tmp2[j] = tmpbuf; + end + always @(posedge clk) + y[i] <= ^tmp2; + end + +endgenerate + +endmodule + +// ------------------------------------------ + +module gen_test2(clk, a, b, y); + +input clk; +input [7:0] a, b; +output reg [8:0] y; + +integer i; +reg [8:0] carry; + +always @(posedge clk) begin + carry[0] = 0; + for (i = 0; i < 8; i = i + 1) begin + casez ({a[i], b[i], carry[i]}) + 3'b?11, 3'b1?1, 3'b11?: + carry[i+1] = 1; + default: + carry[i+1] = 0; + endcase + y[i] = a[i] ^ b[i] ^ carry[i]; + end + y[8] = carry[8]; +end + +endmodule + +// ------------------------------------------ + +module gen_test3(a, b, sel, y, z); + +input [3:0] a, b; +input sel; +output [3:0] y, z; + +genvar i; +generate + for (i=0; i < 2; i=i+1) + assign y[i] = sel ? a[i] : b[i], z[i] = sel ? b[i] : a[i]; + for (i=0; i < 2; i=i+1) begin + if (i == 0) + assign y[2] = sel ? a[2] : b[2]; + else + assign z[2] = sel ? a[2] : b[2]; + case (i) + default: + assign z[3] = sel ? a[3] : b[3]; + 0: + assign y[3] = sel ? a[3] : b[3]; + endcase + end +endgenerate + +endmodule diff --git a/tests/simple/graphtest.v b/tests/simple/graphtest.v new file mode 100644 index 00000000..74788dbb --- /dev/null +++ b/tests/simple/graphtest.v @@ -0,0 +1,34 @@ +module graphtest (A,B,X,Y,Z); + +input [3:0] A; +input [3:0] B; +output reg [3:0] X; +output [9:0] Y; +output [7:0] Z; + +wire [4:0] t; + +assign t[4] = 1'b0; // Constant connects to wire +assign t[2:0] = A[2:0] & { 2'b10, B[3]}; // Concatenation of intermediate wire +assign t[3] = A[2] ^ B[3]; // Bitwise-XOR + +// assign Y[2:0] = 3'b111; +// assign Y[6:3] = A; +// assign Y[9:7] = t[0:2]; +assign Y = {3'b111, A, t[2:0]}; // Direct assignment of concatenation + +assign Z[0] = 1'b0; // Constant connects to PO +assign Z[1] = t[3]; // Intermediate sig connects to PO +assign Z[3:2] = A[2:1]; // PI connects to PO +assign Z[7:4] = {1'b0, B[2:0]}; // Concat of CV and PI connect to PO + +always @* begin + if (A == 4'b1111) begin // All-Const at port (eq) + X = B; + end + else begin + X = 4'b0000; // All-Const at port (mux) + end +end + +endmodule diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v new file mode 100644 index 00000000..123afaea --- /dev/null +++ b/tests/simple/hierarchy.v @@ -0,0 +1,27 @@ + +(* top *) +module top(a, b, y1, y2, y3, y4); +input [3:0] a; +input signed [3:0] b; +output [7:0] y1, y2, y3, y4; + +// this version triggers a bug in Icarus Verilog +// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4); + +// this version is handled correctly by Icarus Verilog +submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4); + +endmodule + +(* gentb_skip *) +module submod(a, b, y1, y2, y3, y4); +parameter c = 0; +parameter [7:0] d = 0; +input [3:0] a, b; +output [7:0] y1, y2, y3, y4; +assign y1 = a; +assign y2 = b; +assign y3 = c; +assign y4 = d; +endmodule + diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v new file mode 100644 index 00000000..3aa59663 --- /dev/null +++ b/tests/simple/i2c_master_tests.v @@ -0,0 +1,62 @@ +// one of my early test cases was the OpenCores I2C master +// This is a collection of stripped down code snippets from +// this core that triggered bugs in early versions of yosys. + +// from i2c_master_bit_ctrl +module i2c_test01(clk, rst, nReset, al); + + input clk, rst, nReset; + output reg al; + + reg cmd_stop; + always @(posedge clk or negedge nReset) + if (~nReset) + cmd_stop <= #1 1'b0; + else if (rst) + cmd_stop <= #1 1'b0; + + always @(posedge clk or negedge nReset) + if (~nReset) + al <= #1 1'b0; + else if (rst) + al <= #1 1'b0; + else + al <= #1 ~cmd_stop; + +endmodule + +// from i2c_master_bit_ctrl +module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt); + + input clk, slave_wait, clk_cnt; + input cmd; + + output reg cmd_stop; + + reg clk_en; + output reg [15:0] cnt; + + always @(posedge clk) + if (~|cnt) + if (~slave_wait) + begin + cnt <= #1 clk_cnt; + clk_en <= #1 1'b1; + end + else + begin + cnt <= #1 cnt; + clk_en <= #1 1'b0; + end + else + begin + cnt <= #1 cnt - 16'h1; + clk_en <= #1 1'b0; + end + + always @(posedge clk) + if (clk_en) + cmd_stop <= #1 cmd; + +endmodule + diff --git a/tests/simple/loops.v b/tests/simple/loops.v new file mode 100644 index 00000000..d7743a42 --- /dev/null +++ b/tests/simple/loops.v @@ -0,0 +1,79 @@ + +// a simple test case extracted from systemcaes (as included in iwls2005) +// this design has latches (or logic loops) for the two temp variables. +// this latches (or logic loops) must be removed in the final synthesis results + +module aes( + // inputs + input [3:0] addroundkey_data_i, + input [3:0] addroundkey_data_reg, + input [3:0] addroundkey_round, + input [3:0] key_i, + input [3:0] keysched_new_key_o, + input [3:0] round, + input addroundkey_start_i, + input keysched_ready_o, + + // outputs + output reg [3:0] keysched_last_key_i, + output reg [3:0] keysched_round_i, + output reg [3:0] next_addroundkey_data_reg, + output reg [3:0] next_addroundkey_round, + output reg [3:0] round_data_var, + output reg keysched_start_i, + output reg next_addroundkey_ready_o +); + +// temp variables +reg [3:0] data_var; +reg [3:0] round_key_var; + +always @* +begin + keysched_start_i = 0; + keysched_round_i = addroundkey_round; + round_data_var = addroundkey_data_reg; + next_addroundkey_data_reg = addroundkey_data_reg; + next_addroundkey_ready_o = 0; + next_addroundkey_round = addroundkey_round; + + if (addroundkey_round == 1 || addroundkey_round == 0) + keysched_last_key_i = key_i; + else + keysched_last_key_i = keysched_new_key_o; + + if (round == 0 && addroundkey_start_i) + begin + data_var = addroundkey_data_i; + round_key_var = key_i; + round_data_var = round_key_var ^ data_var; + next_addroundkey_data_reg = round_data_var; + next_addroundkey_ready_o = 1; + end + else if (addroundkey_start_i && round != 0) + begin + keysched_last_key_i = key_i; + keysched_start_i = 1; + keysched_round_i = 1; + next_addroundkey_round = 1; + end + else if (addroundkey_round != round && keysched_ready_o) + begin + next_addroundkey_round = addroundkey_round + 1; + keysched_last_key_i = keysched_new_key_o; + keysched_start_i = 1; + keysched_round_i = addroundkey_round + 1; + end + else if (addroundkey_round == round && keysched_ready_o) + begin + data_var = addroundkey_data_i; + round_key_var = keysched_new_key_o; + round_data_var = round_key_var ^ data_var; + next_addroundkey_data_reg = round_data_var; + next_addroundkey_ready_o = 1; + next_addroundkey_round = 0; + end +end + +endmodule + diff --git a/tests/simple/macros.v b/tests/simple/macros.v new file mode 100644 index 00000000..7b4d616e --- /dev/null +++ b/tests/simple/macros.v @@ -0,0 +1,244 @@ + +module test_def(a, y); + +`define MSB_LSB_SEP : +`define get_msb(off, len) ((off)+(len)-1) +`define get_lsb(off, len) (off) +`define sel_bits(offset, len) `get_msb(offset, len) `MSB_LSB_SEP `get_lsb(offset, len) + +input [31:0] a; +output [7:0] y; + +assign y = a[`sel_bits(16, 8)]; + +endmodule + +// --------------------------------------------------- + +module test_ifdef(a, y); + +input [2:0] a; +output reg [31:0] y; + +always @* begin + y = 0; + + `undef X + `ifdef X + y = y + 42; + `else + `undef A + `undef B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `undef A + `define B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `undef B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `define B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `undef B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `undef A + `define B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `undef B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `define B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `ifdef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `ifdef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `ifndef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `ifndef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `endif + + `define X + `ifdef X + `undef A + `undef B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `undef A + `define B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `undef B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `define B + `ifdef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `undef B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `undef A + `define B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `undef B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `define B + `ifndef A + y = (y << 1) | a[0]; + `elsif B + y = (y << 1) | a[1]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `ifdef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `ifdef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + // ------------------------------------ + `undef A + `ifndef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `define A + `ifndef A + y = (y << 1) | a[0]; + `else + y = (y << 1) | a[2]; + `endif + `else + y = y + 42; + `endif +end + +endmodule + +`define SIZE 4 // comment supported in this part +module test_comment_in_macro ( din_a, dout_a ); +input [`SIZE-1:0] din_a; +output [`SIZE-1:0] dout_a; +assign dout_a = din_a | `SIZE'ha; +endmodule diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v new file mode 100644 index 00000000..9839fd4a --- /dev/null +++ b/tests/simple/mem2reg.v @@ -0,0 +1,94 @@ + +module mem2reg_test1(in_addr, in_data, out_addr, out_data); + +input [1:0] in_addr, out_addr; +input [3:0] in_data; +output reg [3:0] out_data; + +reg [3:0] array [2:0]; + +always @* begin + array[0] = 0; + array[1] = 23; + array[2] = 42; + array[in_addr] = in_data; + out_data = array[out_addr]; +end + +endmodule + +// ------------------------------------------------------ + +module mem2reg_test2(clk, reset, mode, addr, data); + +input clk, reset, mode; +input [2:0] addr; +output [3:0] data; + +(* mem2reg *) +reg [3:0] mem [0:7]; + +assign data = mem[addr]; + +integer i; + +always @(posedge clk) begin + if (reset) begin + for (i=0; i<8; i=i+1) + mem[i] <= i; + end else + if (mode) begin + for (i=0; i<8; i=i+1) + mem[i] <= mem[i]+1; + end else begin + mem[addr] <= 0; + end +end + +endmodule + +// ------------------------------------------------------ + +// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ +module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); +reg [7:0] dint_c [0:7]; +always @(posedge clk) + begin + {dout_a[0], dint_c[3]} <= din_a; + end +assign dout_b = dint_c[3]; +endmodule + +// ------------------------------------------------------ + +module mem2reg_test4(result1, result2, result3); + output signed [9:0] result1; + output signed [9:0] result2; + output signed [9:0] result3; + + wire signed [9:0] intermediate [0:3]; + + function integer depth2Index; + input integer depth; + depth2Index = depth; + endfunction + + assign intermediate[depth2Index(1)] = 1; + assign intermediate[depth2Index(2)] = 2; + assign intermediate[3] = 3; + assign result1 = intermediate[1]; + assign result2 = intermediate[depth2Index(2)]; + assign result3 = intermediate[depth2Index(3)]; +endmodule + +// ------------------------------------------------------ + +module mem2reg_test5(input ctrl, output out); + wire [0:0] foo[0:0]; + wire [0:0] bar[0:1]; + + assign foo[0] = ctrl; + assign bar[0] = 0, bar[1] = 1; + assign out = bar[foo[0]]; +endmodule + diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v new file mode 100644 index 00000000..9bd38fcb --- /dev/null +++ b/tests/simple/mem_arst.v @@ -0,0 +1,43 @@ + +module MyMem #( + parameter AddrWidth = 4, + parameter DataWidth = 4) ( + (* gentb_constant = 1 *) + input Reset_n_i, + input Clk_i, + input [AddrWidth-1:0] Addr_i, + input [DataWidth-1:0] Data_i, + output [DataWidth-1:0] Data_o, + input WR_i); + + reg [DataWidth-1:0] Data_o; + + localparam Size = 2**AddrWidth; + + (* mem2reg *) + reg [DataWidth-1:0] Mem[Size-1:0]; + + integer i; + + always @(negedge Reset_n_i or posedge Clk_i) + begin + if (!Reset_n_i) + begin + Data_o <= 'bx; + for (i=0; i<Size; i=i+1) + begin + Mem[i] <= 0; + end + end + else + begin + Data_o <= Mem[Addr_i]; + if (WR_i) + begin + Mem[Addr_i] <= Data_i; + end + end + end + +endmodule + diff --git a/tests/simple/memory.v b/tests/simple/memory.v new file mode 100644 index 00000000..f38bdafd --- /dev/null +++ b/tests/simple/memory.v @@ -0,0 +1,309 @@ + +module memtest00(clk, setA, setB, y); + +input clk, setA, setB; +output y; +reg mem [1:0]; + +always @(posedge clk) begin + if (setA) mem[0] <= 0; // this is line 9 + if (setB) mem[0] <= 1; // this is line 10 +end + +assign y = mem[0]; + +endmodule + +// ---------------------------------------------------------- + +module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value); + +input clk, wr_en; +input [3:0] wr_addr, rd_addr; +input [7:0] wr_value; +output reg [7:0] rd_value; + +reg [7:0] data [15:0]; + +always @(posedge clk) + if (wr_en) + data[wr_addr] <= wr_value; + +always @(posedge clk) + rd_value <= data[rd_addr]; + +endmodule + +// ---------------------------------------------------------- + +module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4); + +input clk, setA, setB; +input [1:0] addr; +input [2:0] bit; +output reg y1, y2; +output y3, y4; + +reg [7:0] mem1 [3:0]; + +(* mem2reg *) +reg [7:0] mem2 [3:0]; + +always @(posedge clk) begin + if (setA) begin + mem1[0] <= 10; + mem1[1] <= 20; + mem1[2] <= 30; + mem2[0] <= 17; + mem2[1] <= 27; + mem2[2] <= 37; + end + if (setB) begin + mem1[0] <= 1; + mem1[1] <= 2; + mem1[2] <= 3; + mem2[0] <= 71; + mem2[1] <= 72; + mem2[2] <= 73; + end + y1 <= mem1[addr][bit]; + y2 <= mem2[addr][bit]; +end + +assign y3 = mem1[addr][bit]; +assign y4 = mem2[addr][bit]; + +endmodule + +// ---------------------------------------------------------- + +module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); + +input clk, wr_enable; +input [3:0] wr_addr, wr_data, rd_addr; +output reg [3:0] rd_data; + +reg [3:0] memory [0:15]; + +always @(posedge clk) begin + if (wr_enable) + memory[wr_addr] <= wr_data; + rd_data <= memory[rd_addr]; +end + +endmodule + +// ---------------------------------------------------------- + +module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); + +input clk, wr_enable; +input [3:0] wr_addr, wr_data, rd_addr; +output [3:0] rd_data; + +reg rd_addr_buf; +reg [3:0] memory [0:15]; + +always @(posedge clk) begin + if (wr_enable) + memory[wr_addr] <= wr_data; + rd_addr_buf <= rd_addr; +end + +assign rd_data = memory[rd_addr_buf]; + +endmodule + +// ---------------------------------------------------------- + +module memtest05(clk, addr, wdata, rdata, wen); + +input clk; +input [1:0] addr; +input [7:0] wdata; +output reg [7:0] rdata; +input [3:0] wen; + +reg [7:0] mem [0:3]; + +integer i; +always @(posedge clk) begin + for (i = 0; i < 4; i = i+1) + if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2]; + rdata <= mem[addr]; +end + +endmodule + +// ---------------------------------------------------------- + +module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); + (* gentb_constant=0 *) wire rst; + reg [7:0] test [0:7]; + integer i; + always @(posedge clk) begin + if (rst) begin + for (i=0; i<8; i=i+1) + test[i] <= 0; + end else begin + test[0][2] <= din[1]; + test[0][5] <= test[0][2]; + test[idx][3] <= din[idx]; + test[idx][6] <= test[idx][2]; + test[idx][idx] <= !test[idx][idx]; + end + end + assign dout = test[idx]; +endmodule + +module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); + (* gentb_constant=0 *) wire rst; + reg [7:0] test [0:7]; + integer i; + always @(posedge clk or posedge rst) begin + if (rst) begin + for (i=0; i<8; i=i+1) + test[i] <= 0; + end else begin + test[0][2] <= din[1]; + test[0][5] <= test[0][2]; + test[idx][3] <= din[idx]; + test[idx][6] <= test[idx][2]; + test[idx][idx] <= !test[idx][idx]; + end + end + assign dout = test[idx]; +endmodule + +// ---------------------------------------------------------- + +module memtest07(clk, addr, woffset, wdata, rdata); + +input clk; +input [1:0] addr; +input [3:0] wdata; +input [1:0] woffset; +output reg [7:0] rdata; + +reg [7:0] mem [0:3]; + +integer i; +always @(posedge clk) begin + mem[addr][woffset +: 4] <= wdata; + rdata <= mem[addr]; +end + +endmodule + +// ---------------------------------------------------------- + +module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); + reg [3:0] mem [0:15] [0:15]; + always @(posedge clk) begin + y <= mem[a][b]; + mem[a][b] <= c; + end +endmodule + +// ---------------------------------------------------------- + +module memtest09 ( + input clk, + input [3:0] a_addr, a_din, b_addr, b_din, + input a_wen, b_wen, + output reg [3:0] a_dout, b_dout +); + reg [3:0] memory [10:35]; + + always @(posedge clk) begin + if (a_wen) + memory[10 + a_addr] <= a_din; + a_dout <= memory[10 + a_addr]; + end + + always @(posedge clk) begin + if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen)) + memory[20 + b_addr] <= b_din; + b_dout <= memory[20 + b_addr]; + end +endmodule + +// ---------------------------------------------------------- + +module memtest10(input clk, input [5:0] din, output [5:0] dout); + reg [5:0] queue [0:3]; + integer i; + + always @(posedge clk) begin + queue[0] <= din; + for (i = 1; i < 4; i=i+1) begin + queue[i] <= queue[i-1]; + end + end + + assign dout = queue[3]; +endmodule + +// ---------------------------------------------------------- + +module memtest11(clk, wen, waddr, raddr, wdata, rdata); + input clk, wen; + input [1:0] waddr, raddr; + input [7:0] wdata; + output [7:0] rdata; + + reg [7:0] mem [3:0]; + + assign rdata = mem[raddr]; + + always @(posedge clk) begin + if (wen) + mem[waddr] <= wdata; + else + mem[waddr] <= mem[waddr]; + end +endmodule + +// ---------------------------------------------------------- + +module memtest12 ( + input clk, + input [1:0] adr, + input [1:0] din, + output reg [1:0] q +); + reg [1:0] ram [3:0]; + always@(posedge clk) + {ram[adr], q} <= {din, ram[adr]}; +endmodule + +// ---------------------------------------------------------- + +module memtest13 ( + input clk, rst, + input [1:0] a1, a2, a3, a4, a5, a6, + input [3:0] off1, off2, + input [31:5] din1, + input [3:0] din2, din3, + output reg [3:0] dout1, dout2, + output reg [31:5] dout3 +); + reg [31:5] mem [0:3]; + + always @(posedge clk) begin + if (rst) begin + mem[0] <= 0; + mem[1] <= 0; + mem[2] <= 0; + mem[3] <= 0; + end else begin + mem[a1] <= din1; + mem[a2][14:11] <= din2; + mem[a3][5 + off1 +: 4] <= din3; + dout1 <= mem[a4][12:9]; + dout2 <= mem[a5][5 + off2 +: 4]; + dout3 <= mem[a6]; + end + end +endmodule + diff --git a/tests/simple/multiplier.v b/tests/simple/multiplier.v new file mode 100644 index 00000000..3c0aa1fc --- /dev/null +++ b/tests/simple/multiplier.v @@ -0,0 +1,132 @@ + +// Via http://www.edaplayground.com/s/6/591 +// stackoverflow 20556634 +// http://stackoverflow.com/questions/20556634/how-can-i-iteratively-create-buses-of-parameterized-size-to-connect-modules-also + +// Code your design here +`define macro_args +`define indexed_part_select + +module Multiplier_flat #(parameter M = 4, parameter N = 4)( +input [M-1:0] A, //Input A, size M +input [N-1:0] B, //Input B, size N +output [M+N-1:0] P ); //Output P (product), size M+N + +/* Calculate LSB using Wolfram Alpha + N==3 : http://www.wolframalpha.com/input/?i=0%2C+4%2C+9%2C+15%2C+... + N==4 : http://www.wolframalpha.com/input/?i=0%2C+5%2C+11%2C+18%2C+26%2C+35%2C+... + N==5 : http://www.wolframalpha.com/input/?i=0%2C+6%2C+13%2C+21%2C+30%2C+... + */ +`ifdef macro_args +// initial $display("Use Macro Args"); +`define calc_pp_lsb(n) (((n)-1)*((n)+2*M)/2) +//`define calc_pp_msb(n) (`calc_pp_lsb(n+1)-1) +`define calc_pp_msb(n) ((n**2+(2*M+1)*n-2)/2) +//`define calc_range(n) `calc_pp_msb(n):`calc_pp_lsb(n) +`define calc_pp_range(n) `calc_pp_lsb(n) +: (M+n) + +wire [`calc_pp_msb(N):0] PP; +assign PP[`calc_pp_range(1)] = { 1'b0 , { A & {M{B[0]}} } }; +assign P = PP[`calc_pp_range(N)]; +`elsif indexed_part_select +// initial $display("Use Indexed Part Select"); +localparam MSB = (N**2+(2*M+1)*N-2)/2; +wire [MSB:0] PP; +assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } }; +assign P = PP[MSB -: M+N]; +`else +// initial $display("Use Worst Case"); +localparam MSB = (N**2+(2*M+1)*N-2)/2; +wire [MSB:0] PP; +assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } }; +assign P = PP[MSB : MSB+1-M-N]; +`endif + +genvar i; +generate +for (i=1; i < N; i=i+1) +begin: addPartialProduct + wire [M+i-1:0] gA,gB,gS; + wire Cout; + assign gA = { A & {M{B[i]}} , {i{1'b0}} }; + `ifdef macro_args + assign gB = PP[`calc_pp_range(i)]; + assign PP[`calc_pp_range(i+1)] = {Cout,gS}; + `elsif indexed_part_select + assign gB = PP[(i-1)*(i+2*M)/2 +: M+i]; + assign PP[i*((i+1)+2*M)/2 +: M+i+1] = {Cout,gS}; + `else + localparam LSB = (i-1)*(i+2*M)/2; + localparam MSB = (i**2+(2*M+1)*i-2)/2; + localparam MSB2 = ((i+1)**2+(2*M+1)*(i+1)-2)/2; + assign gB = PP[MSB : LSB]; + assign PP[ MSB2 : MSB+1] = {Cout,gS}; + `endif + RippleCarryAdder#(M+i) adder( .A(gA), .B(gB), .S(gS), .Cin (1'b0), .Cout(Cout) ); +end +endgenerate + +`ifdef macro_args +// Cleanup global space +`undef calc_pp_range +`undef calc_pp_msb +`undef calc_pp_lsb +`endif +endmodule + +module Multiplier_2D #(parameter M = 4, parameter N = 4)( +input [M-1:0] A, //Input A, size M +input [N-1:0] B, //Input B, size N +output [M+N-1:0] P ); //Output P (product), size M+N + +wire [M+N-1:0] PP [N-1:0]; + +// Note: bits PP[0][M+N-1:M+1] are never used. Unused bits are optimized out during synthesis +//assign PP[0][M:0] = { {1'b0} , { A & {M{B[0]}} } }; +//assign PP[0][M+N-1:M+1] = {(N-1){1'b0}}; // uncomment to make probing readable +assign PP[0] = { {N{1'b0}} , { A & {M{B[0]}} } }; +assign P = PP[N-1]; + +genvar i; +generate +for (i=1; i < N; i=i+1) +begin: addPartialProduct + wire [M+i-1:0] gA,gB,gS; wire Cout; + assign gA = { A & {M{B[i]}} , {i{1'b0}} }; + assign gB = PP[i-1][M+i-1:0]; + //assign PP[i][M+i:0] = {Cout,gS}; + //if (i+1<N) assign PP[i][M+N-1:M+i+1] = {(N-i){1'b0}}; // uncomment to make probing readable + assign PP[i] = { {(N-i){1'b0}}, Cout, gS}; + RippleCarryAdder#(M+i) adder( + .A(gA), .B(gB), .S(gS), .Cin(1'b0), .Cout(Cout) ); +end +endgenerate + +//always@* foreach(S[i]) $display("S[%0d]:%b",i,S[i]); + +endmodule + +module RippleCarryAdder#(parameter N = 4)(A,B,Cin,S,Cout); + +input [N-1:0] A; +input [N-1:0] B; +input Cin; +output [N-1:0] S; +output Cout; +wire [N:0] CC; + +assign CC[0] = Cin; +assign Cout = CC[N]; +genvar i; +generate +for (i=0; i < N; i=i+1) +begin: addbit + FullAdder unit(A[i],B[i],CC[i],S[i],CC[i+1]); +end +endgenerate + +endmodule + +module FullAdder(input A,B,Cin, output wire S,Cout); +assign {Cout,S} = A+B+Cin; +endmodule diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v new file mode 100644 index 00000000..1fb1cea5 --- /dev/null +++ b/tests/simple/muxtree.v @@ -0,0 +1,83 @@ + +// test case generated from IWLS 2005 usb_phy core +// (triggered a bug in opt_muxtree pass) + +module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg); + +input clk; +input rst; +input DataOut_i; +input TxValid_i; +output reg hold_reg; + +reg state, next_state; +reg ld_sop_d; +reg ld_data_d; + +always @(posedge clk) + if(ld_sop_d) + hold_reg <= 0; + else + hold_reg <= DataOut_i; + +always @(posedge clk) + if(!rst) state <= 0; + else state <= next_state; + +always @(state or TxValid_i) + begin + next_state = state; + + ld_sop_d = 1'b0; + ld_data_d = 1'b0; + + case(state) // synopsys full_case parallel_case + 0: + if(TxValid_i) + begin + ld_sop_d = 1'b1; + next_state = 1; + end + 1: + if(TxValid_i) + begin + ld_data_d = 1'b1; + next_state = 0; + end + endcase + end + +endmodule + + +// test case inspired by softusb_navre code: +// default not as last case + +module default_cases(a, y); + +input [2:0] a; +output reg [3:0] y; + +always @* begin + case (a) + 3'b000, 3'b111: y <= 0; + default: y <= 4; + 3'b001: y <= 1; + 3'b010: y <= 2; + 3'b100: y <= 3; + endcase +end + +endmodule + + +// test case for muxtree with select on leaves + +module select_leaves(input R, C, D, output reg Q); + always @(posedge C) + if (!R) + Q <= R; + else + Q <= Q ? Q : D ? D : Q; +endmodule + diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v new file mode 100644 index 00000000..569a28ad --- /dev/null +++ b/tests/simple/omsp_dbg_uart.v @@ -0,0 +1,34 @@ + +module omsp_dbg_uart (dbg_clk, dbg_rst, mem_burst, cmd_valid); + +input dbg_clk; +input dbg_rst; +input mem_burst; +output cmd_valid; + +reg [2:0] uart_state; +reg [2:0] uart_state_nxt; + +wire xfer_done; + +parameter RX_SYNC = 3'h0; +parameter RX_CMD = 3'h1; +parameter RX_DATA = 3'h2; + +always @(uart_state or mem_burst) + case (uart_state) + RX_SYNC : uart_state_nxt = RX_CMD; + RX_CMD : uart_state_nxt = mem_burst ? RX_DATA : RX_SYNC; + RX_DATA : uart_state_nxt = RX_SYNC; + default : uart_state_nxt = RX_CMD; + endcase + +always @(posedge dbg_clk or posedge dbg_rst) + if (dbg_rst) uart_state <= RX_SYNC; + else if (xfer_done | mem_burst) uart_state <= uart_state_nxt; + +assign cmd_valid = (uart_state==RX_CMD) & xfer_done; +assign xfer_done = uart_state!=RX_SYNC; + +endmodule + diff --git a/tests/simple/operators.v b/tests/simple/operators.v new file mode 100644 index 00000000..2f0fdb82 --- /dev/null +++ b/tests/simple/operators.v @@ -0,0 +1,121 @@ +module optest(clk, mode, u1, s1, u2, s2, y); + +input clk; +input [6:0] mode; + +input [3:0] u1, u2; +input signed [3:0] s1, s2; + +output reg [7:0] y; + +always @(posedge clk) begin + y <= 8'h42; + case (mode) + 0: y <= u1 << u2; + 1: y <= u1 << s2; + 2: y <= s1 << u2; + 3: y <= s1 << s2; + + 4: y <= u1 >> u2; + 5: y <= u1 >> s2; + 6: y <= s1 >> u2; + 7: y <= s1 >> s2; + + 8: y <= u1 <<< u2; + 9: y <= u1 <<< s2; + 10: y <= s1 <<< u2; + 11: y <= s1 <<< s2; + + 12: y <= u1 >>> u2; + 13: y <= u1 >>> s2; + 14: y <= s1 >>> u2; + 15: y <= s1 >>> s2; + + 16: y <= u1 < u2; + 17: y <= u1 < s2; + 18: y <= s1 < u2; + 19: y <= s1 < s2; + + 20: y <= u1 <= u2; + 21: y <= u1 <= s2; + 22: y <= s1 <= u2; + 23: y <= s1 <= s2; + + 24: y <= u1 == u2; + 25: y <= u1 == s2; + 26: y <= s1 == u2; + 27: y <= s1 == s2; + + 28: y <= u1 != u2; + 29: y <= u1 != s2; + 30: y <= s1 != u2; + 31: y <= s1 != s2; + + 32: y <= u1 >= u2; + 33: y <= u1 >= s2; + 34: y <= s1 >= u2; + 35: y <= s1 >= s2; + + 36: y <= u1 > u2; + 37: y <= u1 > s2; + 38: y <= s1 > u2; + 39: y <= s1 > s2; + + 40: y <= u1 + u2; + 41: y <= u1 + s2; + 42: y <= s1 + u2; + 43: y <= s1 + s2; + + 44: y <= u1 - u2; + 45: y <= u1 - s2; + 46: y <= s1 - u2; + 47: y <= s1 - s2; + + 48: y <= u1 * u2; + 49: y <= u1 * s2; + 50: y <= s1 * u2; + 51: y <= s1 * s2; + + 52: y <= u1 / u2; + 53: y <= u1 / s2; + 54: y <= s1 / u2; + 55: y <= s1 / s2; + + 56: y <= u1 % u2; + 57: y <= u1 % s2; + 58: y <= s1 % u2; + 59: y <= s1 % s2; + + 60: y <= 4'd2 ** u1; + 61: y <= 4'd2 ** s1; + 62: y <= 4'sd2 ** u1; + 63: y <= 4'sd2 ** s1; + + 64: y <= +u1; + 65: y <= -u1; + 66: y <= ~u1; + 67: y <= !u1; + + 68: y <= +s1; + 69: y <= -s1; + 70: y <= ~s1; + 71: y <= !s1; + + 72: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 }; + 73: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 }; + 74: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] }; + 75: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] }; + + 76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] }; + 77: y <= {4{u1[1:0]}}; + 78: y <= {u1, u2} ^ {s1, s2}; + 79: y <= {u1, u2} & {s1, s2}; + + 80: y <= u1[0] ? u1 : u2; + 81: y <= u1[0] ? u1 : s2; + 82: y <= u1[0] ? s1 : u2; + 83: y <= u1[0] ? s1 : s2; + endcase +end + +endmodule diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v new file mode 100644 index 00000000..23cb276f --- /dev/null +++ b/tests/simple/paramods.v @@ -0,0 +1,53 @@ + +module pm_test1(a, b, x, y); + +input [7:0] a, b; +output [7:0] x, y; + +inc #(.step(3)) inc_a (.in(a), .out(x)); +inc #(.width(4), .step(7)) inc_b (b, y); + +endmodule + +// ----------------------------------- + +module pm_test2(a, b, x, y); + +input [7:0] a, b; +output [7:0] x, y; + +inc #(5) inc_a (.in(a), .out(x)); +inc #(4, 7) inc_b (b, y); + +endmodule + +// ----------------------------------- + +module pm_test3(a, b, x, y); + +input [7:0] a, b; +output [7:0] x, y; + +inc inc_a (.in(a), .out(x)); +inc inc_b (b, y); + +defparam inc_a.step = 3; +defparam inc_b.step = 7; +defparam inc_b.width = 4; + +endmodule + +// ----------------------------------- + +module inc(in, out); + +parameter width = 8; +parameter step = 1; + +input [width-1:0] in; +output [width-1:0] out; + +assign out = in + step; + +endmodule + diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v new file mode 100644 index 00000000..7461358a --- /dev/null +++ b/tests/simple/partsel.v @@ -0,0 +1,62 @@ +module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down); +wire [5:0] offset = idx << 2; +assign slice_up = data[offset +: 4]; +assign slice_down = data[offset + 3 -: 4]; +endmodule + +module partsel_test002 ( + input clk, rst, + input [7:0] a, + input [0:7] b, + input [1:0] s, + output [7:0] x1, x2, x3, + output [0:7] x4, x5, x6, + output [7:0] y1, y2, y3, + output [0:7] y4, y5, y6, + output [7:0] z1, z2, z3, + output [0:7] z4, z5, z6, + output [7:0] w1, w2, w3, + output [0:7] w4, w5, w6, + output [7:0] p1, p2, p3, p4, p5, p6, + output [0:7] q1, q2, q3, q4, q5, q6, + output reg [7:0] r1, + output reg [0:7] r2 +); + +assign x1 = a, x2 = a + b, x3 = b; +assign x4 = a, x5 = a + b, x6 = b; +assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3]; +assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3]; +assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3]; +assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3]; +assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6]; +assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6]; +assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2]; +assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2]; + +always @(posedge clk) begin + if (rst) begin + { r1, r2 } = 16'h1337 ^ {a, b}; + end else begin + case (s) + 0: begin + r1[3:0] <= r2[0:3] ^ x1; + r2[4:7] <= r1[7:4] ^ x4; + end + 1: begin + r1[2 +: 3] <= r2[5 -: 3] + x1; + r2[3 +: 3] <= r1[6 -: 3] + x4; + end + 2: begin + r1[6 -: 3] <= r2[3 +: 3] - x1; + r2[7 -: 3] <= r1[4 +: 3] - x4; + end + 3: begin + r1 <= r2; + r2 <= r1; + end + endcase + end +end + +endmodule diff --git a/tests/simple/process.v b/tests/simple/process.v new file mode 100644 index 00000000..8cb4c870 --- /dev/null +++ b/tests/simple/process.v @@ -0,0 +1,84 @@ + +module blocking_cond (in, out); + +input in; +output reg out; +reg tmp; + +always @* begin + tmp = 1; + out = 1'b0; + case (1'b1) + tmp: out = in; + endcase + tmp = 0; +end + +endmodule + +// ------------------------------------------------------------- + +module uut(clk, arst, a, b, c, d, e, f, out1); + +input clk, arst, a, b, c, d, e, f; +output reg [3:0] out1; + +always @(posedge clk, posedge arst) begin + if (arst) + out1 = 0; + else begin + if (a) begin + case ({b, c}) + 2'b00: + out1 = out1 + 9; + 2'b01, 2'b10: + out1 = out1 + 13; + endcase + if (d) begin + out1 = out1 + 2; + out1 = out1 + 1; + end + case ({e, f}) + 2'b11: + out1 = out1 + 8; + 2'b00: + ; + default: + out1 = out1 + 10; + endcase + out1 = out1 ^ 7; + end + out1 = out1 + 14; + end +end + +endmodule + +// ------------------------------------------------------------- + +// extracted from ../asicworld/code_hdl_models_uart.v +// (triggered a bug in the proc_mux pass) +module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt); + +input reset; +input txclk; +input ld_tx_data; + +output reg tx_empty; +output reg [3:0] tx_cnt; + +always @ (posedge txclk) +if (reset) begin + tx_empty <= 1; + tx_cnt <= 0; +end else begin + if (ld_tx_data) begin + tx_empty <= 0; + end + if (!tx_empty) begin + tx_cnt <= tx_cnt + 1; + end +end + +endmodule + diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v new file mode 100644 index 00000000..5b756e6b --- /dev/null +++ b/tests/simple/realexpr.v @@ -0,0 +1,24 @@ + +module demo_001(y1, y2, y3, y4); + output [7:0] y1, y2, y3, y4; + + localparam [7:0] p1 = 123.45; + localparam real p2 = 123.45; + localparam real p3 = 123; + localparam p4 = 123.45; + + assign y1 = p1 + 0.2; + assign y2 = p2 + 0.2; + assign y3 = p3 + 0.2; + assign y4 = p4 + 0.2; +endmodule + +module demo_002(y0, y1, y2, y3); + output [63:0] y0, y1, y2, y3; + + assign y0 = 1'bx >= (-1 * -1.17); + assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0; + assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0; + assign y3 = 1 ? -1 : 'd0; +endmodule + diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v new file mode 100644 index 00000000..5d0c75fa --- /dev/null +++ b/tests/simple/repwhile.v @@ -0,0 +1,36 @@ +module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x); + + function [7:0] mylog2; + input [31:0] value; + begin + mylog2 = 0; + while (value > 0) begin + value = value >> 1; + mylog2 = mylog2 + 1; + end + end + endfunction + + function [31:0] myexp2; + input [7:0] value; + begin + myexp2 = 1; + repeat (value) + myexp2 = myexp2 << 1; + end + endfunction + + reg [7:0] y_table [63:0]; + reg [31:0] x_table [63:0]; + + integer i; + initial begin + for (i = 0; i < 64; i = i+1) begin + y_table[i] <= mylog2(i); + x_table[i] <= myexp2(i); + end + end + + assign y = y_table[a]; + assign x = x_table[a]; +endmodule diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v new file mode 100644 index 00000000..a2fe0005 --- /dev/null +++ b/tests/simple/rotate.v @@ -0,0 +1,48 @@ + +// test case taken from amber23 Verilog code +module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod); + +input [31:0] i_in; +input direction; +input [4:0] shift_amount; +output [31:0] rot_prod; + +// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs. +// Practically a bit higher due to high fanout of "direction". +generate +genvar i, j; + for (i = 0; i < 5; i = i + 1) + begin : netgen + wire [31:0] in; + reg [31:0] out; + for (j = 0; j < 32; j = j + 1) + begin : net + always @* + out[j] = in[j] & (~shift_amount[i] ^ direction) | + in[wrap(j, i)] & (shift_amount[i] ^ direction); + end + end + + // Order is reverted with respect to volatile shift_amount[0] + assign netgen[4].in = i_in; + for (i = 1; i < 5; i = i + 1) + begin : router + assign netgen[i-1].in = netgen[i].out; + end +endgenerate + +// Aliasing +assign rot_prod = netgen[0].out; + +function [4:0] wrap; +input integer pos; +input integer level; +integer out; +begin + out = pos - (1 << level); + wrap = out[4:0]; +end +endfunction + +endmodule + diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh new file mode 100755 index 00000000..aaa1cf94 --- /dev/null +++ b/tests/simple/run-test.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +OPTIND=1 +seed="" # default to no seed specified +while getopts "S:" opt +do + case "$opt" in + S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space + seed="SEED=$arg" ;; + esac +done +shift "$((OPTIND-1))" + +# check for Icarus Verilog +if ! which iverilog > /dev/null ; then + echo "$0: Error: Icarus Verilog 'iverilog' not found." + exit 1 +fi + +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v diff --git a/tests/simple/scopes.v b/tests/simple/scopes.v new file mode 100644 index 00000000..eecc1a0b --- /dev/null +++ b/tests/simple/scopes.v @@ -0,0 +1,63 @@ +module scopes_test_01(input [3:0] k, output reg [15:0] x, y); + function [15:0] func_01; + input [15:0] x, y; + begin + func_01 = x + y; + begin:blk + reg [15:0] x; + x = y; + func_01 = func_01 ^ x; + end + func_01 = func_01 ^ x; + end + endfunction + + function [15:0] func_02; + input [15:0] x, y; + begin + func_02 = x - y; + begin:blk + reg [15:0] func_02; + func_02 = 0; + end + end + endfunction + + task task_01; + input [3:0] a; + reg [15:0] y; + begin + y = a * 23; + x = x + y; + end + endtask + + task task_02; + input [3:0] a; + begin:foo + reg [15:0] x, z; + x = y; + begin:bar + reg [15:0] x; + x = 77 + a; + z = -x; + end + y = x ^ z; + end + endtask + + always @* begin + x = func_01(11, 22); + y = func_02(33, 44); + task_01(k); + task_02(k); + begin:foo + reg [15:0] y; + y = x; + y = y + k; + x = y; + end + x = func_01(y, x); + y = func_02(y, x); + end +endmodule diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v new file mode 100644 index 00000000..8bba4a4b --- /dev/null +++ b/tests/simple/signedexpr.v @@ -0,0 +1,18 @@ +module signed_test01(a, b, xu, xs, yu, ys, zu, zs); + +input signed [1:0] a; +input signed [2:0] b; +output [3:0] xu, xs; +output [3:0] yu, ys; +output zu, zs; + +assign xu = (a + b) + 3'd0; +assign xs = (a + b) + 3'sd0; + +assign yu = {a + b} + 3'd0; +assign ys = {a + b} + 3'sd0; + +assign zu = a + b != 3'd0; +assign zs = a + b != 3'sd0; + +endmodule diff --git a/tests/simple/sincos.v b/tests/simple/sincos.v new file mode 100644 index 00000000..b3124337 --- /dev/null +++ b/tests/simple/sincos.v @@ -0,0 +1,124 @@ +// File: design.v +// Generated by MyHDL 0.8 +// Date: Tue Dec 3 04:33:14 2013 + + +module d ( + cos_z0, + sin_z0, + done, + z0, + start, + clock, + reset +); +// Sine and cosine computer. +// +// This module computes the sine and cosine of an input angle. The +// floating point numbers are represented as integers by scaling them +// up with a factor corresponding to the number of bits after the point. +// +// Ports: +// ----- +// cos_z0: cosine of the input angle +// sin_z0: sine of the input angle +// done: output flag indicated completion of the computation +// z0: input angle +// start: input that starts the computation on a posedge +// clock: clock input +// reset: reset input + +output signed [19:0] cos_z0; +reg signed [19:0] cos_z0; +output signed [19:0] sin_z0; +reg signed [19:0] sin_z0; +output done; +reg done; +input signed [19:0] z0; +input start; +input clock; +input reset; + +(* gentb_constant = 1'b0 *) +wire reset; + +always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR + reg [5-1:0] i; + reg [1-1:0] state; + reg signed [20-1:0] dz; + reg signed [20-1:0] dx; + reg signed [20-1:0] dy; + reg signed [20-1:0] y; + reg signed [20-1:0] x; + reg signed [20-1:0] z; + if (reset) begin + state = 1'b0; + cos_z0 <= 1; + sin_z0 <= 0; + done <= 1'b0; + x = 0; + y = 0; + z = 0; + i = 0; + end + else begin + case (state) + 1'b0: begin + if (start) begin + x = 159188; + y = 0; + z = z0; + i = 0; + done <= 1'b0; + state = 1'b1; + end + end + 1'b1: begin + dx = $signed(y >>> $signed({1'b0, i})); + dy = $signed(x >>> $signed({1'b0, i})); + case (i) + 0: dz = 205887; + 1: dz = 121542; + 2: dz = 64220; + 3: dz = 32599; + 4: dz = 16363; + 5: dz = 8189; + 6: dz = 4096; + 7: dz = 2048; + 8: dz = 1024; + 9: dz = 512; + 10: dz = 256; + 11: dz = 128; + 12: dz = 64; + 13: dz = 32; + 14: dz = 16; + 15: dz = 8; + 16: dz = 4; + 17: dz = 2; + default: dz = 1; + endcase + if ((z >= 0)) begin + x = x - dx; + y = y + dy; + z = z - dz; + end + else begin + x = x + dx; + y = y - dy; + z = z + dz; + end + if ((i == (19 - 1))) begin + cos_z0 <= x; + sin_z0 <= y; + state = 1'b0; + done <= 1'b1; + end + else begin + i = i + 1; + end + end + endcase + end +end + +endmodule diff --git a/tests/simple/subbytes.v b/tests/simple/subbytes.v new file mode 100644 index 00000000..04269a99 --- /dev/null +++ b/tests/simple/subbytes.v @@ -0,0 +1,82 @@ + +// test taken from systemcaes from iwls2005 + +module subbytes_00(clk, reset, start_i, decrypt_i, data_i, ready_o, data_o, sbox_data_o, sbox_data_i, sbox_decrypt_o); + +input clk; +input reset; +input start_i; +input decrypt_i; +input [31:0] data_i; +output ready_o; +output [31:0] data_o; +output [7:0] sbox_data_o; +input [7:0] sbox_data_i; +output sbox_decrypt_o; + +reg ready_o; +reg [31:0] data_o; +reg [7:0] sbox_data_o; +reg sbox_decrypt_o; + +reg [1:0] state; +reg [1:0] next_state; +reg [31:0] data_reg; +reg [31:0] next_data_reg; +reg next_ready_o; + +always @(posedge clk or negedge reset) +begin + if (!reset) begin + data_reg = 0; + state = 0; + ready_o = 0; + end else begin + data_reg = next_data_reg; + state = next_state; + ready_o = next_ready_o; + end +end + +reg [31:0] data_i_var, data_reg_128; +reg [7:0] data_array [3:0]; +reg [7:0] data_reg_var [3:0]; + +always @(decrypt_i or start_i or state or data_i or sbox_data_i or data_reg) +begin + data_i_var = data_i; + + data_array[0] = data_i_var[ 31: 24]; + data_array[1] = data_i_var[ 23: 16]; + data_array[2] = data_i_var[ 15: 8]; + data_array[3] = data_i_var[ 7: 0]; + + data_reg_var[0] = data_reg[ 31: 24]; + data_reg_var[1] = data_reg[ 23: 16]; + data_reg_var[2] = data_reg[ 15: 8]; + data_reg_var[3] = data_reg[ 7: 0]; + + sbox_decrypt_o = decrypt_i; + sbox_data_o = data_array[state]; + next_state = state; + next_data_reg = data_reg; + + next_ready_o = 0; + data_o = data_reg; + + if (state) begin + if (start_i) begin + next_state = 1; + end + end else begin + data_reg_var[state] = sbox_data_i; + data_reg_128[ 31: 24] = data_reg_var[0]; + data_reg_128[ 23: 16] = data_reg_var[1]; + data_reg_128[ 15: 8] = data_reg_var[2]; + data_reg_128[ 7: 0] = data_reg_var[3]; + next_data_reg = data_reg_128; + next_state = state + 1; + end +end + +endmodule diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v new file mode 100644 index 00000000..fa50c1d5 --- /dev/null +++ b/tests/simple/task_func.v @@ -0,0 +1,122 @@ + +module task_func_test01(clk, a, b, c, x, y, z, w); + +input clk; +input [7:0] a, b, c; +output reg [7:0] x, y, z, w; + +function [7:0] sum_shift; +input [3:0] s1, s2, s3; +sum_shift = s1 + (s2 << 2) + (s3 << 4); +endfunction + +task reset_w; +w = 0; +endtask + +task add_to; +output [7:0] out; +input [7:0] in; +out = out + in; +endtask + +always @(posedge clk) begin + x = sum_shift(a, b, c); + y = sum_shift(a[7:4], b[5:2], c[3:0]); + z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3); + + reset_w; + add_to(w, x); + add_to(w, y); + add_to(w, z); +end + +endmodule + +// ------------------------------------------------------------------- + +module task_func_test02(clk, a, b, c, x, y, z, w); + +input clk; +input [7:0] a, b, c; +output reg [7:0] x, y, z, w; + +function [7:0] sum_shift(input [3:0] s1, s2, s3); +sum_shift = s1 + (s2 << 2) + (s3 << 4); +endfunction + +task reset_w; +w = 0; +endtask + +task add_to(output [7:0] out, input [7:0] in); +out = out + in; +endtask + +always @(posedge clk) begin + x = sum_shift(a, b, c); + y = sum_shift(a[7:4], b[5:2], c[3:0]); + z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3); + + reset_w; + add_to(w, x); + add_to(w, y); + add_to(w, z); +end + +endmodule + +// ------------------------------------------------------------------- + +module task_func_test03(input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); + assign dout_a = test(din_a,din_b); + function [7:0] test; + input [7:0] a; + input [7:0] b; + begin : TEST + integer i; + for (i = 0; i <= 7; i = i + 1) + test[i] = a[i] & b[i]; + end + endfunction +endmodule + +// ------------------------------------------------------------------- + +module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4); + parameter p = 23; + parameter px = 42; + function [7:0] test1; + input [7:0] i; + parameter p = 42; + begin + test1 = i + p; + end + endfunction + function [7:0] test2; + input [7:0] i; + parameter p2 = p+42; + begin + test2 = i + p2; + end + endfunction + function [7:0] test3; + input [7:0] i; + begin + test3 = i + p; + end + endfunction + function [7:0] test4; + input [7:0] i; + parameter px = p + 13; + parameter p3 = px - 37; + parameter p4 = p3 ^ px; + begin + test4 = i + p4; + end + endfunction + assign out1 = test1(in); + assign out2 = test2(in); + assign out3 = test3(in); + assign out4 = test4(in); +endmodule diff --git a/tests/simple/undef_eqx_nex.v b/tests/simple/undef_eqx_nex.v new file mode 100644 index 00000000..b0178677 --- /dev/null +++ b/tests/simple/undef_eqx_nex.v @@ -0,0 +1,11 @@ +module undef_eqx_nex(y); +output [7:0] y; +assign y[0] = 0/0; +assign y[1] = 0/1; +assign y[2] = 0/0 == 32'bx; +assign y[3] = 0/0 != 32'bx; +assign y[4] = 0/0 === 32'bx; +assign y[5] = 0/0 !== 32'bx; +assign y[6] = 0/1 === 32'bx; +assign y[7] = 0/1 !== 32'bx; +endmodule diff --git a/tests/simple/usb_phy_tests.v b/tests/simple/usb_phy_tests.v new file mode 100644 index 00000000..bc45e71a --- /dev/null +++ b/tests/simple/usb_phy_tests.v @@ -0,0 +1,36 @@ + +// from usb_rx_phy +module usb_phy_test01(clk, rst, rx_en, fs_ce); + +input clk, rst; +input rx_en; +output reg fs_ce; +reg [1:0] dpll_next_state; +reg [1:0] dpll_state; + +always @(posedge clk) + dpll_state <= rst ? 0 : dpll_next_state; + +always @* + begin + fs_ce = 1'b0; + case(dpll_state) + 2'h0: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h1; + 2'h1:begin + fs_ce = 1'b1; + if(rx_en) dpll_next_state = 2'h3; + else dpll_next_state = 2'h2; + end + 2'h2: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h3; + 2'h3: + if(rx_en) dpll_next_state = 2'h0; + else dpll_next_state = 2'h0; + endcase + end + +endmodule + diff --git a/tests/simple/values.v b/tests/simple/values.v new file mode 100644 index 00000000..afcd251f --- /dev/null +++ b/tests/simple/values.v @@ -0,0 +1,44 @@ + +module test_signed(a, b, c, d, y); + +input [3:0] a, b, c; +input signed [3:0] d; +output reg [7:0] y; + +always @* begin + if (a && b) + y = c; + else + y = d; +end + +endmodule + +module test_const(a, y); + +input [3:0] a; +output reg [28:0] y; + +always @* + case (a) + 4'b0000: y = 0; + 4'b0001: y = 11; + 4'b0010: y = 222; + 4'b0011: y = 3456; + 4'b0100: y = 'b10010010; + 4'b0101: y = 'h123abc; + 4'b0110: y = 'o1234567; + 4'b0111: y = 'd3456789; + 4'b1000: y = 16'b10010010; + 4'b1001: y = 16'h123abc; + 4'b1010: y = 16'o1234567; + 4'b1011: y = 16'd3456789; + 4'b1100: y = { "foo", "bar" }; + 4'b1101: y = "foobarfoobarfoobar"; + 4'b1110: y = 16'h1; + 4'b1111: y = a; + default: y = 'bx; + endcase + +endmodule + diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v new file mode 100644 index 00000000..3bb3cf99 --- /dev/null +++ b/tests/simple/vloghammer.v @@ -0,0 +1,82 @@ + +// test cases found using vloghammer +// https://github.com/cliffordwolf/VlogHammer + +module test01(a, y); + input [7:0] a; + output [3:0] y; + assign y = ~a >> 4; +endmodule + +module test02(a, y); + input signed [3:0] a; + output signed [4:0] y; + assign y = (~a) >> 1; +endmodule + +module test03(a, b, y); + input [2:0] a; + input signed [1:0] b; + output y; + assign y = ~(a >>> 1) == b; +endmodule + +module test04(a, y); + input a; + output [1:0] y; + assign y = ~(a - 1'b0); +endmodule + +// .. this test triggers a bug in Xilinx ISIM. +// module test05(a, y); +// input a; +// output y; +// assign y = 12345 >> {a, 32'd0}; +// endmodule + +// .. this test triggers a bug in Icarus Verilog. +// module test06(a, b, c, y); +// input signed [3:0] a; +// input signed [1:0] b; +// input signed [1:0] c; +// output [5:0] y; +// assign y = (a >> b) >>> c; +// endmodule + +module test07(a, b, y); + input signed [1:0] a; + input signed [2:0] b; + output y; + assign y = 2'b11 != a+b; +endmodule + +module test08(a, b, y); + input [1:0] a; + input [1:0] b; + output y; + assign y = a == ($signed(b) >>> 1); +endmodule + +module test09(a, b, c, y); + input a; + input signed [1:0] b; + input signed [2:0] c; + output [3:0] y; + assign y = a ? b : c; +endmodule + +module test10(a, b, c, y); + input a; + input signed [1:0] b; + input signed [2:0] c; + output y; + assign y = ^(a ? b : c); +endmodule + +// module test11(a, b, y); +// input signed [3:0] a; +// input signed [3:0] b; +// output signed [5:0] y; +// assign y = -(5'd27); +// endmodule + diff --git a/tests/simple/wreduce.v b/tests/simple/wreduce.v new file mode 100644 index 00000000..ba548438 --- /dev/null +++ b/tests/simple/wreduce.v @@ -0,0 +1,9 @@ +module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z); + assign x = -$signed({1'b0, a}); + assign y = $signed({1'b0, a}) + $signed({1'b0, b}); + assign z = x ^ y; +endmodule + +module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w); + assign x = a - b, y = a * b, z = a >> b, w = a << b; +endmodule |