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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Added tests/simple/graphtest.vClifford Wolf2015-11-30
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-12
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
* Bugfix in memory_dffClifford Wolf2015-10-31
* Improvements in wreduceClifford Wolf2015-10-31
* Another block of spelling fixesLarry Doolittle2015-08-14
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Various fixes for memories with offsetsClifford Wolf2015-02-14
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit test caseClifford Wolf2015-02-14
* improvements in muxtree/select_leaves testClifford Wolf2015-01-18
* Improvements in opt_muxtreeClifford Wolf2015-01-18
* Added support for task and function args in parenthesesClifford Wolf2014-10-27
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* Little steps in realmath test benchClifford Wolf2014-06-21
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-15
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
* Added support for math functionsClifford Wolf2014-06-14
* Added realexpr.v test caseClifford Wolf2014-06-14
* added tests for new verilog featuresClifford Wolf2014-06-07
* Added tests/simple/repwhile.vClifford Wolf2014-06-06
* Progress in Verific bindingsClifford Wolf2014-03-17
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Added multiplier test case from eda playgroundClifford Wolf2013-12-18
* Added elsif preproc supportClifford Wolf2013-12-18
* Added support for macro argumentsClifford Wolf2013-12-18
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Fix in sincos testbench genClifford Wolf2013-12-04
* Added sincos test caseClifford Wolf2013-12-04