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Author
Age
*
Added "test_cell" command
Clifford Wolf
2014-07-29
*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
*
Fixed Verilog pre-processor for files with no trailing newline
Clifford Wolf
2014-07-29
*
Bugfix in simlib.v for iverilog
Clifford Wolf
2014-07-29
*
Allow "hierarchy -generate" for $__ cells
Clifford Wolf
2014-07-29
*
Added "techmap -map %{design-name}"
Clifford Wolf
2014-07-29
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Removed left over debug code
Clifford Wolf
2014-07-28
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
*
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf
2014-07-28
*
Fixed RTLIL code generator for part select of parameter
Clifford Wolf
2014-07-28
*
Fixed width detection for part selects
Clifford Wolf
2014-07-28
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added std::initializer_list<> constructor to SigSpec
Clifford Wolf
2014-07-28
*
Added cover() to all SigSpec constructors
Clifford Wolf
2014-07-28
*
Fixed signdness detection of expressions with bit- and part-selects
Clifford Wolf
2014-07-28
*
Improvements in tests/vloghtb
Clifford Wolf
2014-07-28
*
Added techmap -extern
Clifford Wolf
2014-07-27
*
Added proper Design->addModule interface
Clifford Wolf
2014-07-27
*
Added topological sorting to techmap
Clifford Wolf
2014-07-27
*
Added SigPool::check(bit)
Clifford Wolf
2014-07-27
*
Small improvements in PerformanceTimer API
Clifford Wolf
2014-07-27
*
Fixed bug in opt_clean
Clifford Wolf
2014-07-27
*
Improved performance of opt_const on large modules
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpecConstIterator
Clifford Wolf
2014-07-27
*
Fixed a bug in opt_clean and some RTLIL API usage cleanups
Clifford Wolf
2014-07-27
*
Added log_cmd_error_expection
Clifford Wolf
2014-07-27
*
Fixed verific bindings for new RTLIL api
Clifford Wolf
2014-07-27
*
Fixed ilang parser for new RTLIL API
Clifford Wolf
2014-07-27
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Added RTLIL::Module::wire(id) and cell(id) lookup functions
Clifford Wolf
2014-07-27
*
Added RTLIL::Design::modules()
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Added conversion from ObjRange to std::vector and std::set
Clifford Wolf
2014-07-27
*
Added RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf
2014-07-27
*
Using std::move() in SigSpec move constructor
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpec move constructor and move assignment operator
Clifford Wolf
2014-07-27
*
Mostly cosmetic changes to rtlil.h
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
New message for completion of build
Clifford Wolf
2014-07-26
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added tests/various/.gitignore
Clifford Wolf
2014-07-26
*
Added tests/various/submod_extract.ys
Clifford Wolf
2014-07-26
*
Added support for here documents
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
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