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Age
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
*
Updated command-reference-manual.tex
Clifford Wolf
2013-11-23
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AppNote 010 typo fixes and corrections
Clifford Wolf
2013-11-23
*
AppNote 010 progress
Clifford Wolf
2013-11-23
*
Improved handling of techmap special wires
Clifford Wolf
2013-11-23
*
Improved handling of initialized registers
Clifford Wolf
2013-11-23
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
*
Making prograss on Appnote 010
Clifford Wolf
2013-11-23
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Progress on AppNote 010
Clifford Wolf
2013-11-22
*
Started to write on AppNote 010: Verilog to BLIF
Clifford Wolf
2013-11-22
*
Updated command-reference-manual.tex
Clifford Wolf
2013-11-22
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Some driver changes/fixes
Clifford Wolf
2013-11-22
*
Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf
2013-11-22
*
Added more performance measurement infrastructure
Clifford Wolf
2013-11-22
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
*
Improved make rules for profiling and debugging
Clifford Wolf
2013-11-22
*
Updated abc
Clifford Wolf
2013-11-21
*
Implemented $_DFFSR_ expression generator in verilog backend
Clifford Wolf
2013-11-21
*
Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Fixed a bug in "add -global_input"
Clifford Wolf
2013-11-21
*
Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
*
Fixed ilang parser: memory width
Clifford Wolf
2013-11-20
*
Added "add" command (only wires for now)
Clifford Wolf
2013-11-20
*
Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
*
Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf
2013-11-20
*
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
*
Updated TODOs in README file
Clifford Wolf
2013-11-20
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
*
Added "make config-sudo"
Clifford Wolf
2013-11-19
*
Install simlib in datdir
Clifford Wolf
2013-11-19
*
Large improvements in yosys-config
Clifford Wolf
2013-11-19
*
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
*
Renamed temp module generated by "abc" pass from "logic" to "netlist"
Clifford Wolf
2013-11-19
*
Added additional mem2reg testcase
Clifford Wolf
2013-11-18
*
Fixed two bugs in mem2reg functionality in AST frontend
Clifford Wolf
2013-11-18
*
Added dumping of attributes in AST frontend
Clifford Wolf
2013-11-18
*
Fixed parsing of default cases when not last case
Clifford Wolf
2013-11-18
*
Fixed mem2reg for reg usage outside always block
Clifford Wolf
2013-11-18
*
Added commented-out osu025 maping commands to cmos techmap example
Clifford Wolf
2013-11-18
*
Added -v<level> option and some minor driver cleanups
Clifford Wolf
2013-11-17
*
Renamed ABCHGPULL to ABCPULL in Makefile
Clifford Wolf
2013-11-16
*
Improved building of yosys-abc
Clifford Wolf
2013-11-13
*
Fixed abc pass blif parser for constant bits
Clifford Wolf
2013-11-13
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