yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed oom bug in ilang parser	Clifford Wolf	2015-11-29
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*	Fixed performance bug in ilang parser	Clifford Wolf	2015-11-27
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-11-26
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\| *	Added PRIM_DLATCHRS support to verific front-end	Clifford Wolf	2015-11-24
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* \|	Removed dangling ';' in rtlil.h	Clifford Wolf	2015-11-26
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* \|	Added ice40_ffinit pass	Clifford Wolf	2015-11-26
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*	Fixed WE/RE usage in iCE40 BRAM mapping	Clifford Wolf	2015-11-24
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*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23
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*	Added torder command	Clifford Wolf	2015-11-19
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*	Fixed performance bug in Verific importer	Clifford Wolf	2015-11-16
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*	Changes for Verific 3.16_484_32_151112	Clifford Wolf	2015-11-12
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*	Link to vlsitechnology.org for liberty files	Clifford Wolf	2015-11-12
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*	More bugfixes in handling of parameters in tasks and functions	Clifford Wolf	2015-11-12
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*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11
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*	Added "abc -g"	Clifford Wolf	2015-11-10
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*	Merge pull request #97 from zeldin/master	Clifford Wolf	2015-11-08
\|\ \| \| \| \|	Fix a segfault in dffinit when the value has too few bits
\| *	Fix a segfault in dffinit when the value has too few bits	Marcus Comstedt	2015-11-08
\|/ \| \| \| \|	The code was already trying to add the required number of bits, but fell one short of the mark.
*	Added "singleton" pass	Clifford Wolf	2015-11-07
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*	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	Clifford Wolf	2015-11-06
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*	Bugfix in mapping $tribuf to $_TBUF_	Clifford Wolf	2015-11-05
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*	Bugfix in memory_dff	Clifford Wolf	2015-10-31
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*	Improvements in wreduce	Clifford Wolf	2015-10-31
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*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30
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*	Improved SigMap performance	Clifford Wolf	2015-10-28
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*	Improvements in new SigMap	Clifford Wolf	2015-10-28
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*	Use mfp<> in equiv_mark	Clifford Wolf	2015-10-27
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*	Removed old SigMap implementation	Clifford Wolf	2015-10-27
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*	Added hashlib::mfp and new SigMap	Clifford Wolf	2015-10-27
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-25
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*	Major refactoring of equiv_struct	Clifford Wolf	2015-10-25
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25
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*	Added "equiv_add -cell"	Clifford Wolf	2015-10-25
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*	equiv_struct now creates equiv_merged attributes	Clifford Wolf	2015-10-25
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-24
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*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24
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*	improvement in "stat"	Clifford Wolf	2015-10-24
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*	Fixed driver conflict handling (various cmds)	Clifford Wolf	2015-10-24
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*	equiv_purge bugfix, using SigChunk in Yosys namespace	Clifford Wolf	2015-10-24
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*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24
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*	Added equiv_mark command	Clifford Wolf	2015-10-23
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*	Disabled "Skipping blackbox module" msg in show command	Clifford Wolf	2015-10-23
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*	Added support for ":" as comment symbol after ;-parsing	Clifford Wolf	2015-10-23
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*	Also merge $equiv cells in equiv_struct	Clifford Wolf	2015-10-23
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*	Improvements in equiv_struct	Clifford Wolf	2015-10-23
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*	Added equiv_purge	Clifford Wolf	2015-10-22
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*	Added equiv_struct command	Clifford Wolf	2015-10-21
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*	Improved inout handling in equiv_make	Clifford Wolf	2015-10-21
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*	Progress on cell help messages	Clifford Wolf	2015-10-20
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*	Progress on cell help messages	Clifford Wolf	2015-10-17
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*	Progress in yosys-smtbmc	Clifford Wolf	2015-10-15
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