yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Include unistd.h in svgview.cpp (required for getcwd() function)	Martin Schmölzer	2013-11-28
\| \| \| \| \| \|	This fixes compilation on Arch Linux, which otherwise fails. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Added QGraphicsWebView to yosys-svgviewer	Clifford Wolf	2013-11-28
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*	Updated ABC to 9241719523f6	Clifford Wolf	2013-11-28
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*	Added some svgviewer code for possible future switch to QGraphicsWebView	Clifford Wolf	2013-11-27
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-11-27
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\| *	Set version number to 0.1.0+	Clifford Wolf	2013-11-27
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* \|	Tighter integration of ABC build	Clifford Wolf	2013-11-27
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*	Started implementing undef support in "sat" command	Clifford Wolf	2013-11-25
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*	Bugfixes in new "stat" command	Clifford Wolf	2013-11-25
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*	Added "stat" command	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Added ezsat vec_const() api	Clifford Wolf	2013-11-25
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*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25
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*	Removed undef feature from ezsat api	Clifford Wolf	2013-11-25
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
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*	Added simplemap pass	Clifford Wolf	2013-11-24
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
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*	Added techmap -D and -I options	Clifford Wolf	2013-11-24
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
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*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24
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*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24
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*	Updated TODOs	Clifford Wolf	2013-11-24
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*	Fixed xilinx/example_sim_counter test bench	Clifford Wolf	2013-11-24
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*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
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*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
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*	Removed now obsolete test cases	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
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*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24
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*	Fixed "make install" dependencies	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Updated command-reference-manual.tex	Clifford Wolf	2013-11-23
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*	AppNote 010 typo fixes and corrections	Clifford Wolf	2013-11-23
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*	AppNote 010 progress	Clifford Wolf	2013-11-23
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*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23
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*	Improved handling of initialized registers	Clifford Wolf	2013-11-23
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
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*	Making prograss on Appnote 010	Clifford Wolf	2013-11-23
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*	Progress on AppNote 010	Clifford Wolf	2013-11-22
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*	Started to write on AppNote 010: Verilog to BLIF	Clifford Wolf	2013-11-22
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*	Updated command-reference-manual.tex	Clifford Wolf	2013-11-22
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Some driver changes/fixes	Clifford Wolf	2013-11-22
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*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22
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*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
\| \| \| \|	flex)
*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22
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