| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-02-13 |
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| | * | Fixed MXE ABC build | Clifford Wolf | 2016-02-13 |
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| * | | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 |
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| * | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 |
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| * | Support for more Verific primitives (patch I got per email) | Clifford Wolf | 2016-02-13 |
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| * | Updated ABC | Clifford Wolf | 2016-02-08 |
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| * | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 |
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| * | Updated ABC | Clifford Wolf | 2016-02-07 |
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| * | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 |
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| * | Bugfix in Verific front-end | Clifford Wolf | 2016-02-03 |
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| * | Updated verific build instructions | Clifford Wolf | 2016-02-02 |
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| * | Improved dffsr2dff pass | Clifford Wolf | 2016-02-02 |
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| * | Added dffsr2dff | Clifford Wolf | 2016-02-02 |
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| * | Added addBufGate module method | Clifford Wolf | 2016-02-02 |
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| * | Use alphanumerical order instead of idstring idx in opt_clean compare_signals() | Clifford Wolf | 2016-02-02 |
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| * | Added CodeOfConduct | Clifford Wolf | 2016-02-01 |
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| * | Updated ABC to hg rev ee212a9e94df | Clifford Wolf | 2016-02-01 |
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| * | Progress in cell library documentation | Clifford Wolf | 2016-02-01 |
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| * | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 |
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| * | Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs) | Clifford Wolf | 2016-02-01 |
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| * | SigMap performance improvement | Clifford Wolf | 2016-02-01 |
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| * | hashlib mfp<> performance improvements | Clifford Wolf | 2016-02-01 |
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| * | Added reserve() method to haslib classes and | Clifford Wolf | 2016-01-31 |
| | | | | | calculate hashtable size based on entries capacity, not size | ||
| * | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys | Clifford Wolf | 2016-01-31 |
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| | * | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
| | | | | | | | | | | | | | | | | | Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop. | ||
| | * | rtlil: speed up SigSpec::sort_and_unify() | Rick Altherr | 2016-01-31 |
| | | | | | | | | | | | | | | | | | | | | | std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique(). | ||
| | * | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
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| | * | genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵ | Rick Altherr | 2016-01-31 |
| | | | | | | | | | removeSignalFromCaseTree() | ||
| | * | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 |
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| * | | More clang sanitizer stuff | Clifford Wolf | 2016-01-31 |
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| * | Meaningless coding style change | Clifford Wolf | 2016-01-31 |
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| * | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys | Clifford Wolf | 2016-01-31 |
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| | * | rtlil: rewrite remove2() to avoid copying | Rick Altherr | 2016-01-30 |
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| | * | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 |
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| | * | rtlil: change IdString comparison operators to take references instead of copies | Rick Altherr | 2016-01-29 |
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| * | | Addedd clang sanitizers | Clifford Wolf | 2016-01-31 |
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| * | Added "equiv_struct -fwonly" | Clifford Wolf | 2016-01-08 |
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| * | Bugfixes in equiv_struct | Clifford Wolf | 2016-01-08 |
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| * | Added "submod -copy" | Clifford Wolf | 2016-01-08 |
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| * | Added "write_blif -cname" mode | Clifford Wolf | 2016-01-06 |
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| * | Added "equiv_struct -maxiter <N>" | Clifford Wolf | 2016-01-06 |
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| * | Added "equiv_add -try" mode | Clifford Wolf | 2016-01-06 |
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| * | Fixed "splitnets -ports" for hierarchical designs | Clifford Wolf | 2015-12-22 |
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| * | Re-run ice40_opt in "synth_ice40 -abc2" | Clifford Wolf | 2015-12-22 |
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| * | Improvements in ice40_opt | Clifford Wolf | 2015-12-22 |
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| * | Bugfix in ice40_ffinit | Clifford Wolf | 2015-12-22 |
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| * | Improved ice40_ffinit | Clifford Wolf | 2015-12-22 |
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| * | Run opt_const before check in default scripts | Clifford Wolf | 2015-12-22 |
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| * | Added %R select expression | Clifford Wolf | 2015-12-20 |
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| * | Various improvements in BLIF front-end | Clifford Wolf | 2015-12-20 |
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index : yosys | |
| Debian dgit repo for package yosys |
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