yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added support for inverter chains to opt_const	Clifford Wolf	2014-02-02
*	Added RTLIL::SigSpec::to_single_sigbit()	Clifford Wolf	2014-02-02
*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02
*	Added constant-clock case to opt_rmdff	Clifford Wolf	2014-02-02
*	presentation progress	Clifford Wolf	2014-02-02
*	Added show -notitle option	Clifford Wolf	2014-02-02
*	Added delete command	Clifford Wolf	2014-02-02
*	Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax	Clifford Wolf	2014-02-02
*	presentation progress	Clifford Wolf	2014-02-02
*	presentation progress	Clifford Wolf	2014-02-02
*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02
*	Fixed a bug in miter command	Clifford Wolf	2014-02-01
*	Added sat -show-inputs and -show-outputs	Clifford Wolf	2014-02-01
*	Added show -color support for cells and finished show -label implementation	Clifford Wolf	2014-02-01
*	Fixed comment/eol parsing in ilang frontend	Clifford Wolf	2014-02-01
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Added note about SystemVerilog assert statement to README	Clifford Wolf	2014-02-01
*	Added miter command	Clifford Wolf	2014-02-01
*	Progress on presentation	Clifford Wolf	2014-01-31
*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
*	presentation progress	Clifford Wolf	2014-01-30
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
*	Added yosys -H for command list	Clifford Wolf	2014-01-30
*	presentation progress	Clifford Wolf	2014-01-29
*	presentation progress	Clifford Wolf	2014-01-29
*	Tiny change in example script in README	Clifford Wolf	2014-01-29
*	Added -h command line option	Clifford Wolf	2014-01-29
*	Added test comments to techlibs/cmos/cmos_cells.lib	Clifford Wolf	2014-01-29
*	Updated ABC to hg rev e6b09e1	Clifford Wolf	2014-01-29
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29
*	presentation progress	Clifford Wolf	2014-01-28
*	Renamed manual/FILES_* directories	Clifford Wolf	2014-01-28
*	Progress on presentation	Clifford Wolf	2014-01-28
*	Progress on presentation	Clifford Wolf	2014-01-27
*	Added first presentation slides	Clifford Wolf	2014-01-27
*	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	Clifford Wolf	2014-01-26
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\| *	root bug corrected	Ahmed Irfan	2014-01-25
* \|	Merge pull request #21 from hansiglaser/master	Clifford Wolf	2014-01-25
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\| * \|	enabled multiple "-map" for the extract pass	Johann Glaser	2014-01-25
\| * \|	beautified write_intersynth	Johann Glaser	2014-01-25
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* \|	Added support for // comments in liberty parser	Clifford Wolf	2014-01-25
* \|	Merge branch 'btor'	Clifford Wolf	2014-01-24
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\| *	removed regex include	Ahmed Irfan	2014-01-24
\| *	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24
\| *	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24
\| *	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24
\| *	Restored Makefile	Clifford Wolf	2014-01-24
\| *	Restored IdString::check()	Clifford Wolf	2014-01-24
\| *	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor	Clifford Wolf	2014-01-24
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