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* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-29
* Preserve important attributes in splitnetsClifford Wolf2015-04-29
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-29
* ice40_opt bugfixClifford Wolf2015-04-27
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-27
* Added simplemap $lut supportClifford Wolf2015-04-27
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-27
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-26
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-25
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-25
* Updated ABC to hg rev 779de2de1481Clifford Wolf2015-04-25
* More iCE40 bram improvementsClifford Wolf2015-04-25
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-24
* iCE40 bram progressClifford Wolf2015-04-24
* iCE40 bram tests and fixesClifford Wolf2015-04-24
* Added ice40 bram supportClifford Wolf2015-04-24
* Fixed memory_share for unconditional write with part select to memoryClifford Wolf2015-04-22
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-19
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-19
* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-18
* Added ice40 test_arithClifford Wolf2015-04-18
* Added ice40 SB_CARRY supportClifford Wolf2015-04-18
* don't consider blackbox modules in "sat" commandClifford Wolf2015-04-18
* Improved handling of init values in opt_rmdffClifford Wolf2015-04-18
* Bugfix for $_DFF_?_ in "dff2dffe -direct-match"Clifford Wolf2015-04-17
* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-17
* Improved "maccmap" help messageClifford Wolf2015-04-16
* A "#" does start a comment, not a label.Clifford Wolf2015-04-16
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-16
* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-16
* Added simple ice40 dff testsClifford Wolf2015-04-16
* improved ice40 dff cell mappingClifford Wolf2015-04-16
* Added "dff2dffe -direct-match"Clifford Wolf2015-04-16
* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-14
* more cells in ice40 cell libraryClifford Wolf2015-04-14
* Added "splice -wires"Clifford Wolf2015-04-13
* Added handling of bool-output cells to "wreduce"Clifford Wolf2015-04-13
* Improved xilinx "bram1" testClifford Wolf2015-04-09
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Added back-end auto-detect for .edif and .jsonClifford Wolf2015-04-09
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Fixed const2big performance bugClifford Wolf2015-04-09
* techmap code cleanupClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for "file names with blanks"Clifford Wolf2015-04-08
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
* Added %M and %C select operatorsClifford Wolf2015-04-07
* Added "pmuxtree" commandClifford Wolf2015-04-07
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