index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
*
Added .barbuf support to abc BLIF parser
Clifford Wolf
2015-05-13
*
changed file() to open() in python scripts
Clifford Wolf
2015-05-11
*
Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
|
\
|
*
Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
*
|
Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
|
/
*
Merge pull request #62 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-10
|
\
|
*
Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
|
*
Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
|
*
Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
|
/
*
Fixed memory_unpack for initialized memories
Clifford Wolf
2015-04-29
*
Preserve important attributes in splitnets
Clifford Wolf
2015-04-29
*
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
*
ice40_opt bugfix
Clifford Wolf
2015-04-27
*
iCE40: SB_CARRY const fold -> unmap SB_LUT
Clifford Wolf
2015-04-27
*
Added simplemap $lut support
Clifford Wolf
2015-04-27
*
Added iCE40 const folding support for SB_CARRY
Clifford Wolf
2015-04-27
*
Initialization support for all iCE40 bram modes
Clifford Wolf
2015-04-26
*
initialized iCE40 brams (mode 0)
Clifford Wolf
2015-04-25
*
improved iCE40 SB_RAM40_4K simulation model
Clifford Wolf
2015-04-25
*
Updated ABC to hg rev 779de2de1481
Clifford Wolf
2015-04-25
*
More iCE40 bram improvements
Clifford Wolf
2015-04-25
*
Improved attributes API and handling of "src" attributes
Clifford Wolf
2015-04-24
*
iCE40 bram progress
Clifford Wolf
2015-04-24
*
iCE40 bram tests and fixes
Clifford Wolf
2015-04-24
*
Added ice40 bram support
Clifford Wolf
2015-04-24
*
Fixed memory_share for unconditional write with part select to memory
Clifford Wolf
2015-04-22
*
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
Clifford Wolf
2015-04-19
*
Verilog front-end: define `BLACKBOX in -lib mode
Clifford Wolf
2015-04-19
*
added sync reset to ice40 test_ffs.sh
Clifford Wolf
2015-04-18
*
Added ice40 test_arith
Clifford Wolf
2015-04-18
*
Added ice40 SB_CARRY support
Clifford Wolf
2015-04-18
*
don't consider blackbox modules in "sat" command
Clifford Wolf
2015-04-18
*
Improved handling of init values in opt_rmdff
Clifford Wolf
2015-04-18
*
Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
Clifford Wolf
2015-04-17
*
Added mapping of synchronous set/reset to iCE40 flow
Clifford Wolf
2015-04-17
*
Improved "maccmap" help message
Clifford Wolf
2015-04-16
*
A "#" does start a comment, not a label.
Clifford Wolf
2015-04-16
*
Changed ice40 ICESTORM_CARRYCONST port name
Clifford Wolf
2015-04-16
*
Fixed "dff2dffe -direct-match"
Clifford Wolf
2015-04-16
*
Added simple ice40 dff tests
Clifford Wolf
2015-04-16
*
improved ice40 dff cell mapping
Clifford Wolf
2015-04-16
*
Added "dff2dffe -direct-match"
Clifford Wolf
2015-04-16
*
use "hierarchy -auto-top" in synth_ice40
Clifford Wolf
2015-04-14
*
more cells in ice40 cell library
Clifford Wolf
2015-04-14
*
Added "splice -wires"
Clifford Wolf
2015-04-13
*
Added handling of bool-output cells to "wreduce"
Clifford Wolf
2015-04-13
*
Improved xilinx "bram1" test
Clifford Wolf
2015-04-09
*
Added memory_bram "make_outreg" feature
Clifford Wolf
2015-04-09
*
Added back-end auto-detect for .edif and .json
Clifford Wolf
2015-04-09
*
Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
[next]