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Debian dgit repo for package yosys
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Age
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Progress on AppNote 011
Clifford Wolf
2013-11-29
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Using RTLIL::id2cstr for prompt printing
Clifford Wolf
2013-11-29
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Added dump -m and -n options
Clifford Wolf
2013-11-29
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Progress on AppNote 011
Clifford Wolf
2013-11-28
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Merge pull request #17 from mschmoelzer/master
Clifford Wolf
2013-11-28
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Include unistd.h in svgview.cpp (required for getcwd() function)
Martin Schmölzer
2013-11-28
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Fixed temp net name generation in rtlil process generator for abbreviated nam...
Clifford Wolf
2013-11-28
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Added pattern support to "ls" command
Clifford Wolf
2013-11-28
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Improved ID matching scheme in select (and thus for all commands)
Clifford Wolf
2013-11-28
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Fixes and improvements in "show" command
Clifford Wolf
2013-11-28
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More progress on AppNote 011
Clifford Wolf
2013-11-28
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Added "src" attribute to processes
Clifford Wolf
2013-11-28
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Started writing appnote 011
Clifford Wolf
2013-11-28
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Added support for "show -pause" and "show -format dot"
Clifford Wolf
2013-11-28
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Added QGraphicsWebView to yosys-svgviewer
Clifford Wolf
2013-11-28
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Updated ABC to 9241719523f6
Clifford Wolf
2013-11-28
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Added some svgviewer code for possible future switch to QGraphicsWebView
Clifford Wolf
2013-11-27
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-11-27
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Set version number to 0.1.0+
Clifford Wolf
2013-11-27
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Tighter integration of ABC build
Clifford Wolf
2013-11-27
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Started implementing undef support in "sat" command
Clifford Wolf
2013-11-25
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Bugfixes in new "stat" command
Clifford Wolf
2013-11-25
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Added "stat" command
Clifford Wolf
2013-11-25
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Improvements in satgen undef handling
Clifford Wolf
2013-11-25
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Improvements in satgen undef handling
Clifford Wolf
2013-11-25
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Added ezsat vec_const() api
Clifford Wolf
2013-11-25
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Started implementing undef handling in satgen
Clifford Wolf
2013-11-25
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Removed undef feature from ezsat api
Clifford Wolf
2013-11-25
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Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
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Added simplemap pass
Clifford Wolf
2013-11-24
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
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Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
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Added techmap -D and -I options
Clifford Wolf
2013-11-24
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Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
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Added "techmap -share_map" option
Clifford Wolf
2013-11-24
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Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
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Updated TODOs
Clifford Wolf
2013-11-24
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Fixed xilinx/example_sim_counter test bench
Clifford Wolf
2013-11-24
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Added proper dumping of signed/unsigned parameters to verilog backend
Clifford Wolf
2013-11-24
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Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
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Removed now obsolete test cases
Clifford Wolf
2013-11-24
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Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
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Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
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Added modelsim support to autotest
Clifford Wolf
2013-11-24
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Fixed "flatten" top-module detection: Only use on fully selected designs
Clifford Wolf
2013-11-24
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Fixed "make install" dependencies
Clifford Wolf
2013-11-24
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Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
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Updated command-reference-manual.tex
Clifford Wolf
2013-11-23
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AppNote 010 typo fixes and corrections
Clifford Wolf
2013-11-23
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AppNote 010 progress
Clifford Wolf
2013-11-23
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