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*
Changes in techmap $__alu interface
Clifford Wolf
2014-08-16
*
Added "opt -fast"
Clifford Wolf
2014-08-16
*
Added log_spacer()
Clifford Wolf
2014-08-16
*
Bugfix in iopadmap
Clifford Wolf
2014-08-15
*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
Removed old doc references to $safe_pmux
Clifford Wolf
2014-08-15
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
*
Added Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf
2014-08-15
*
document "techmap -map %<design-name>"
Clifford Wolf
2014-08-15
*
Fixed bug in "read_verilog -ignore_redef"
Clifford Wolf
2014-08-15
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
*
Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
*
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf
2014-08-14
*
Fixed line numbers when using here-doc macros
Clifford Wolf
2014-08-14
*
Fixed handling of task outputs
Clifford Wolf
2014-08-14
*
Simplified $__arraymul techmap rule
Clifford Wolf
2014-08-14
*
Added module->ports
Clifford Wolf
2014-08-14
*
Refactoring of CellType class
Clifford Wolf
2014-08-14
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
*
Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
*
Added "abc -D" for setting delay target
Clifford Wolf
2014-08-14
*
Updated ABC to 4935c2b946de
Clifford Wolf
2014-08-14
*
Added techmap support for actual lookahead carry unit
Clifford Wolf
2014-08-13
*
Preparations for lookahead ALU support in techmap.v
Clifford Wolf
2014-08-13
*
Filter ANSI escape sequences from ABC output
Clifford Wolf
2014-08-13
*
New interface for $__alu in techmap.v
Clifford Wolf
2014-08-13
*
Added support for non-standard """ macro bodies
Clifford Wolf
2014-08-13
*
Fixed handling of constant-true branches in proc_clean
Clifford Wolf
2014-08-12
*
Added test_verific mode to tests/fsm/generate.py
Clifford Wolf
2014-08-12
*
Fixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf
2014-08-12
*
Fixed building verific bindings
Clifford Wolf
2014-08-12
*
Added multi-dim memory test (requires iverilog git head)
Clifford Wolf
2014-08-12
*
Another build fix by americanrouter (via reddit)
Clifford Wolf
2014-08-11
*
Fixed FSM mapping for multiple reset-like signals
Clifford Wolf
2014-08-10
*
Fixed "share" for complex scenarios with never-active cells
Clifford Wolf
2014-08-09
*
Do not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf
2014-08-09
*
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf
2014-08-09
*
Improved FSM tests
Clifford Wolf
2014-08-08
*
Another fsm_extract bugfix
Clifford Wolf
2014-08-08
*
Fixed "fsm -export"
Clifford Wolf
2014-08-08
*
Fixed sharing of reduce operator
Clifford Wolf
2014-08-08
*
Fixed fsm_extract for wreduced muxes
Clifford Wolf
2014-08-08
*
Added FSM test bench
Clifford Wolf
2014-08-08
*
Added "sat -prove-skip"
Clifford Wolf
2014-08-08
*
Fixed build with gcc-4.6
Clifford Wolf
2014-08-07
*
Use "-keepdc" in "miter -equiv -flatten"
Clifford Wolf
2014-08-07
*
Also allow "module foobar(input foo, output bar, ...);" syntax
Clifford Wolf
2014-08-07
*
Added adff2dff.v (for techmap -share_map)
Clifford Wolf
2014-08-07
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
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