yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added SMV back-end 'test_cells.sh' script	Clifford Wolf	2015-08-12
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*	Use MEMID as name for $mem cell	Clifford Wolf	2015-08-09
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*	Remove some very strange whitespace in btor.cc (by Larry Doolittle)	Clifford Wolf	2015-08-05
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*	Bugfix in SMV back-end for partially unassigned wires	Clifford Wolf	2015-08-05
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*	Added $assert support to SMV back-end	Clifford Wolf	2015-08-04
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*	Improvements in BLIF back-end	Clifford Wolf	2015-07-29
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Added init support to SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-18
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*	Progress in SMV back-end	Clifford Wolf	2015-06-17
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*	Progress in SMV back-end	Clifford Wolf	2015-06-17
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*	Progress in SMV back-end	Clifford Wolf	2015-06-16
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*	Progress in SMV back-end	Clifford Wolf	2015-06-15
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*	Progress in SMV back-end	Clifford Wolf	2015-06-15
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*	Added "write_smv" skeleton	Clifford Wolf	2015-06-15
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*	Removed debug code from write_smt2	Clifford Wolf	2015-06-14
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*	Added write_smt2 -mem	Clifford Wolf	2015-06-14
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*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11
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*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11
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*	AigMaker refactoring	Clifford Wolf	2015-06-10
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*	Added "json -aig"	Clifford Wolf	2015-06-10
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*	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08
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*	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04
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*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24
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*	Some fixes for $mem in verilog back-end	Clifford Wolf	2015-05-20
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*	Merge pull request #63 from wluker/verilog-backend-mem	Clifford Wolf	2015-05-11
\|\ \| \| \| \|	Fixed bug in $mem cell verilog code generation.
\| *	Fixed bug in $mem cell verilog code generation.	luke whittlesey	2015-05-11
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* \|	Disabled broken $mem support in verilog backend	Clifford Wolf	2015-05-10
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*	Made changes recommended by Clifford Wolf ...	luke whittlesey	2015-05-10
\| \| \| \| \| \|	Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
*	Verilog backend for $mem cells should now be able to handle different	luke whittlesey	2015-05-08
\| \| \| \|	write-enable bits and RD_TRANSPARENT parameter settings.
*	Added support for $mem cells in the verilog backend.	luke whittlesey	2015-05-07
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*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09
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*	Removed "techmap -share_map" (use "-map +/filename" instead)	Clifford Wolf	2015-04-08
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*	Added "port_directions" to write_json output	Clifford Wolf	2015-04-06
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*	Added "init" attribute support to verilog backend	Clifford Wolf	2015-04-04
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*	Update README	Ahmed Irfan	2015-04-03
\| \| \|	corrected url
*	Delete btor.ys	Ahmed Irfan	2015-04-03
\| \| \|	.ys script not needed
*	Update README	Ahmed Irfan	2015-04-03
\| \| \|	pmux cell is implemented
*	separated memory next from write cell	Ahmed Irfan	2015-04-03
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*	Added Verilog backend $dffsr support	Clifford Wolf	2015-03-18
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*	Documentation for JSON format, added attributes	Clifford Wolf	2015-03-06
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*	Json bugfix	Clifford Wolf	2015-03-03
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*	Json backend improvements	Clifford Wolf	2015-03-03
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*	Added write_blif -attr	Clifford Wolf	2015-03-02
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*	Added JSON backend	Clifford Wolf	2015-03-02
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*	Added $assume support to write_smt2	Clifford Wolf	2015-02-26
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*	Minor "write_smt2" help msg change	Clifford Wolf	2015-02-22
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*	Added "<mod>_a" and "<mod>_i" to write_smt2 output	Clifford Wolf	2015-02-22
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