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simplify.cc
Commit message (
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Author
Age
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Fixed generate-for (and disabled double warning for auto-wire)
Clifford Wolf
2013-12-04
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Added support for $clog2 system function
Clifford Wolf
2013-12-04
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Various improvements in support for generate statements
Clifford Wolf
2013-12-04
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Added support for local regs in named blocks
Clifford Wolf
2013-12-04
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Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
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Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
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Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
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Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
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Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
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Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
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Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
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Fixed two bugs in mem2reg functionality in AST frontend
Clifford Wolf
2013-11-18
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Fixed mem2reg for reg usage outside always block
Clifford Wolf
2013-11-18
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Fixed handling of different signedness in power operands
Clifford Wolf
2013-11-08
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Implemented const folding of ternary op with undef select
Clifford Wolf
2013-11-08
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Fixed handling of power operator
Clifford Wolf
2013-11-07
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Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
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Disabled const folding of ternary op when select is undef
Clifford Wolf
2013-11-07
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Fixed sign handling in constants
Clifford Wolf
2013-11-07
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Fixed const folding in corner cases with parameters
Clifford Wolf
2013-11-07
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Fixed at_zero evaluation of dynamic ranges
Clifford Wolf
2013-11-07
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Various fixes for correct parameter support
Clifford Wolf
2013-11-07
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Another fix for early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
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Fixed const folding of ternary operator
Clifford Wolf
2013-11-04
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Use proper bit width ans sign extension for const folding
Clifford Wolf
2013-11-04
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Fixes for early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
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further improved early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
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Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...
Clifford Wolf
2013-11-02
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Various ast changes for early expression width detection (prep for constfold ...
Clifford Wolf
2013-11-02
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Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
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Added support for notif0/notif1 primitives
Johann Glaser
2013-08-20
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Added support for bufif0/bufif1 primitives
Clifford Wolf
2013-08-19
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Improved ast dumping (ast/verilog frontend)
Clifford Wolf
2013-08-19
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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Fixes and improvements in AST const folding
Clifford Wolf
2013-06-10
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Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
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Merge branch 'bugfix'
Clifford Wolf
2013-05-16
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*
Fixed synthesis of functions in latched blocks
Clifford Wolf
2013-05-16
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Improvements and bugfixes for generate blocks with local signals
Clifford Wolf
2013-03-26
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Fixed handling of unconditional generate blocks
Clifford Wolf
2013-03-26
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/
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
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Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
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Another fix in mem2reg ast simplify logic
Clifford Wolf
2013-03-24
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Improved mem2reg handling in ast simplifier
Clifford Wolf
2013-03-24
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Tiny fixes to verilog parser
Clifford Wolf
2013-03-23
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
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Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
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initial import
Clifford Wolf
2013-01-05