| Commit message (Expand) | Author | Age |
* | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 |
* | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 |
* | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 |
* | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 |
* | SigSpec refactoring: Added RTLIL::SigSpecIterator | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: added RTLIL::SigSpec::operator[] | Clifford Wolf | 2014-07-22 |
* | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 |
* | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
* | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 |
* | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 |
* | Added SIZE() macro | Clifford Wolf | 2014-07-20 |
* | Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit> | Clifford Wolf | 2014-07-18 |
* | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 |
* | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 |
* | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 |
* | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 |
* | Added RTLIL::Module::add... helper methods | Clifford Wolf | 2014-03-10 |
* | Added generic RTLIL::SigSpec::parse_sel() with support for selection variables | Clifford Wolf | 2014-02-06 |
* | Added RTLIL::SigSpec::to_single_sigbit() | Clifford Wolf | 2014-02-02 |
* | Added select -assert-none and -assert-any | Clifford Wolf | 2014-01-17 |
* | Added RTLIL::SigSpec::optimized() API | Clifford Wolf | 2014-01-03 |
* | Added $bu0 cell (for easy correct $eq/$ne mapping) | Clifford Wolf | 2013-12-28 |
* | Added proper === and !== support in constant expressions | Clifford Wolf | 2013-12-27 |
* | Fixed uninitialized const flags bug | Clifford Wolf | 2013-12-07 |
* | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 |
* | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 |
* | Added module->avail_parameters (for advanced techmap features) | Clifford Wolf | 2013-11-24 |
* | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 |
* | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 |
* | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 |
* | Added SigBit struct and refactored RTLIL::SigSpec::extract | Clifford Wolf | 2013-11-22 |
* | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 |
* | Improved user-friendliness of "sat" and "eval" expression parsing | Clifford Wolf | 2013-11-09 |
* | Renamed extend_un0() to extend_u0() and use it in genrtlil | Clifford Wolf | 2013-11-07 |
* | Fixed type of sign extension in opt_const $eq/$ne handling | Clifford Wolf | 2013-11-07 |
* | Added design->full_selection() helper method | Clifford Wolf | 2013-10-27 |
* | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 |
* | Fixed handling of boolean attributes (kernel) | Clifford Wolf | 2013-10-24 |
* | Changed NEW_WIRE API to return the wire, not the signal | Clifford Wolf | 2013-10-18 |
* | Added RTLIL NEW_WIRE macro | Clifford Wolf | 2013-10-18 |
* | Added techmap -opt mode | Clifford Wolf | 2013-08-09 |