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Author
Age
*
Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
Clifford Wolf
2014-01-03
*
Added RTLIL::SigSpec::optimized() API
Clifford Wolf
2014-01-03
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
*
Added SAT undef model for $pmux and $safe_pmux
Clifford Wolf
2014-01-02
*
Major rewrite of "freduce" command
Clifford Wolf
2014-01-02
*
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
Clifford Wolf
2013-12-31
*
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
Clifford Wolf
2013-12-29
*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
*
Fixed sat handling of $eqx and $nex with unequal port widths
Clifford Wolf
2013-12-27
*
Small cleanup in SatGen
Clifford Wolf
2013-12-27
*
Fixed sat handling of $eqx and $nex cells
Clifford Wolf
2013-12-27
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
*
Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
*
Added log_dump() API
Clifford Wolf
2013-12-20
*
Added "sat" undef support and "sat -set-init" options
Clifford Wolf
2013-12-07
*
Fixed uninitialized const flags bug
Clifford Wolf
2013-12-07
*
Fixes and improvements in RTLIL::SigSpec::parse
Clifford Wolf
2013-12-07
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Added Pass:call_newsel API
Clifford Wolf
2013-12-02
*
Added "history" command
Clifford Wolf
2013-12-02
*
Using RTLIL::id2cstr for prompt printing
Clifford Wolf
2013-11-29
*
Improvements in satgen undef handling
Clifford Wolf
2013-11-25
*
Improvements in satgen undef handling
Clifford Wolf
2013-11-25
*
Started implementing undef handling in satgen
Clifford Wolf
2013-11-25
*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
*
Some driver changes/fixes
Clifford Wolf
2013-11-22
*
Added more performance measurement infrastructure
Clifford Wolf
2013-11-22
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Added -v<level> option and some minor driver cleanups
Clifford Wolf
2013-11-17
*
Added information on all internal cell types to internal checker
Clifford Wolf
2013-11-11
*
Call internal checker more often
Clifford Wolf
2013-11-10
*
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
*
Added verification of SAT model to "eval -vloghammer_report" command
Clifford Wolf
2013-11-09
*
More undef-propagation related fixes
Clifford Wolf
2013-11-08
*
Removed debug log from const_pow()
Clifford Wolf
2013-11-08
*
Fixed handling of power operator
Clifford Wolf
2013-11-07
*
Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
*
Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
*
Improved undef handling in == and != for ConstEval
Clifford Wolf
2013-11-06
*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
*
Fixed handling of undef values in POS cells in ConstEval
Clifford Wolf
2013-11-06
*
Fixed handling of undef values in MUX select input in ConstEval
Clifford Wolf
2013-11-06
*
Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
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