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kernel
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Author
Age
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
*
Some driver changes/fixes
Clifford Wolf
2013-11-22
*
Added more performance measurement infrastructure
Clifford Wolf
2013-11-22
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Added -v<level> option and some minor driver cleanups
Clifford Wolf
2013-11-17
*
Added information on all internal cell types to internal checker
Clifford Wolf
2013-11-11
*
Call internal checker more often
Clifford Wolf
2013-11-10
*
Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
*
Added verification of SAT model to "eval -vloghammer_report" command
Clifford Wolf
2013-11-09
*
More undef-propagation related fixes
Clifford Wolf
2013-11-08
*
Removed debug log from const_pow()
Clifford Wolf
2013-11-08
*
Fixed handling of power operator
Clifford Wolf
2013-11-07
*
Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
*
Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
*
Improved undef handling in == and != for ConstEval
Clifford Wolf
2013-11-06
*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
*
Fixed handling of undef values in POS cells in ConstEval
Clifford Wolf
2013-11-06
*
Fixed handling of undef values in MUX select input in ConstEval
Clifford Wolf
2013-11-06
*
Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
*
Fixed sign handling in const eval of sshl and sshr
Clifford Wolf
2013-11-05
*
Write yosys version to output files
Clifford Wolf
2013-11-03
*
Fixed get_share_file_name() for installed yosys
Clifford Wolf
2013-10-27
*
Added API and Makefile rules for share/ files
Clifford Wolf
2013-10-27
*
Added design->full_selection() helper method
Clifford Wolf
2013-10-27
*
Fixed handling of boolean attributes (passes)
Clifford Wolf
2013-10-24
*
Fixed handling of boolean attributes (kernel)
Clifford Wolf
2013-10-24
*
Changed NEW_WIRE API to return the wire, not the signal
Clifford Wolf
2013-10-18
*
Added RTLIL NEW_WIRE macro
Clifford Wolf
2013-10-18
*
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
Clifford Wolf
2013-10-18
*
Added $sr, $dffsr and $dlatch cell types
Clifford Wolf
2013-10-18
*
Added version info to yosys command and added -V option
Clifford Wolf
2013-08-20
*
Implemented same div-by-zero behavior as found in other synthesis tools
Clifford Wolf
2013-08-15
*
Fixed signed div/mod in const eval (rounding and stuff)
Clifford Wolf
2013-08-15
*
Added sat -ignore_div_by_zero switch
Clifford Wolf
2013-08-15
*
Added eval -brute_force_equiv_checker_x mode
Clifford Wolf
2013-08-15
*
Added SAT support for $div and $mod cells
Clifford Wolf
2013-08-11
*
Added "clean -purge" and ";;;" support
Clifford Wolf
2013-08-11
*
Added ";;" as shortcut for "; clean;"
Clifford Wolf
2013-08-11
*
Added techmap -opt mode
Clifford Wolf
2013-08-09
*
Some fixes to improve determinism
Clifford Wolf
2013-08-09
*
Fixed SigPool::del() method
Clifford Wolf
2013-08-06
*
Added proper deallocation of history buffer
Clifford Wolf
2013-08-06
*
Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
*
Added "help -write-web-command-reference-manual"
Clifford Wolf
2013-07-26
*
Added $lut cells and abc lut mapping support
Clifford Wolf
2013-07-23
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