Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 |
* | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 |
* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
* | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 |
* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 |
* | Added delete {-input|-output|-port} | Clifford Wolf | 2014-02-09 |
* | Bugfix in delete command | Clifford Wolf | 2014-02-09 |
* | Added delete command | Clifford Wolf | 2014-02-02 |