Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 |
* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 |
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
* | Changes to "memory" pass for new $memwr/$mem WR_EN interface | Clifford Wolf | 2014-07-16 |
* | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 |
* | Added automatic memid generation to memory_unpack command | Clifford Wolf | 2014-01-17 |
* | Added memory_unpack command | Clifford Wolf | 2014-01-17 |