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Author
Age
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
*
Added sat -show-regs, -show-public, -show-all
Clifford Wolf
2015-08-18
*
Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
*
Added "miter -assert"
Clifford Wolf
2015-07-25
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Added logic-loop error handling to freduce
Clifford Wolf
2015-06-30
*
don't consider blackbox modules in "sat" command
Clifford Wolf
2015-04-18
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Fixed "sat -initsteps" off-by-one bug
Clifford Wolf
2015-02-22
*
Added "sat -stepsize" and "sat -tempinduct-step"
Clifford Wolf
2015-02-21
*
sat docu change
Clifford Wolf
2015-02-21
*
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
Clifford Wolf
2015-02-21
*
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
Clifford Wolf
2015-02-21
*
Fixed basecase init for "sat -tempinduct"
Clifford Wolf
2015-02-21
*
Replaced ezDefaultSAT with ezSatPtr
Clifford Wolf
2015-02-21
*
format fixes in "sat -dump_json"
Clifford Wolf
2015-02-19
*
Added "sat -dump_json" (WaveJSON format)
Clifford Wolf
2015-02-19
*
Improved an error message
Clifford Wolf
2015-01-28
*
Added "sat -show-ports"
Clifford Wolf
2015-01-27
*
Moved equiv stuff to passes/equiv/
Clifford Wolf
2015-01-22
*
Progress in equiv_simple
Clifford Wolf
2015-01-21
*
Added equiv_simple
Clifford Wolf
2015-01-19
*
Added equiv_status
Clifford Wolf
2015-01-19
*
Added equiv_make command
Clifford Wolf
2015-01-19
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
Clifford Wolf
2014-10-10
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
*
Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
*
azonenberg: Make dump_vcd save model when temporal induction fails due to ste...
Clifford Wolf
2014-08-24
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
Fixed "share" for complex scenarios with never-active cells
Clifford Wolf
2014-08-09
*
Do not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf
2014-08-09
*
Fixed sharing of reduce operator
Clifford Wolf
2014-08-08
*
Added "sat -prove-skip"
Clifford Wolf
2014-08-08
*
Use "-keepdc" in "miter -equiv -flatten"
Clifford Wolf
2014-08-07
*
Fixed "share" for memory read ports
Clifford Wolf
2014-08-03
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed modwalker.h to modtools.h
Clifford Wolf
2014-07-31
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
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