summaryrefslogtreecommitdiff
path: root/passes/techmap/simplemap.cc
Commit message (Expand)AuthorAge
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-29
* Added new cell types to manualClifford Wolf2013-12-28
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Using simplemap mappers from techmapClifford Wolf2013-11-24
* Added simplemap passClifford Wolf2013-11-24