Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Added $assert cell | Clifford Wolf | 2014-01-19 |
* | Fixed $lut simlib model for a wider range of tools | Clifford Wolf | 2014-01-18 |
* | More changes to simlib to make it friendlier to a wider range of tools | Clifford Wolf | 2014-01-18 |
* | Fixed a type in $mem model in simlib.v | Clifford Wolf | 2014-01-18 |
* | Added $bu0 cell to simlib.v | Clifford Wolf | 2014-01-18 |
* | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 |
* | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 |
* | Cleanups and bugfixes in response to new internal cell checker | Clifford Wolf | 2013-11-11 |
* | Added $sr, $dffsr and $dlatch cell types | Clifford Wolf | 2013-10-18 |
* | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |