yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added $tribuf and $_TBUF_ sim models	Clifford Wolf	2015-08-16
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*	Added $tribuf and $_TBUF_ cell types	Clifford Wolf	2015-08-16
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*	Another block of spelling fixes	Larry Doolittle	2015-08-14
\| \| \| \|	Smaller this time
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
\| \| \| \|	This is based on work done by Larry Doolittle
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
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*	Added "synth -nofsm"	Clifford Wolf	2015-07-02
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Added "synth -nordff -noalumacc"	Clifford Wolf	2015-06-15
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*	Added simplemap $lut support	Clifford Wolf	2015-04-27
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*	make all vector-size related integer params in $mem sim model signed	Clifford Wolf	2015-04-05
\| \| \| \| \| \|	this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05
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*	Added $assume cell type	Clifford Wolf	2015-02-26
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*	Added "stat" to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Added final checks to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Smaller default parameters in $mem simlib model	Clifford Wolf	2015-02-15
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14
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*	Added $meminit cell type	Clifford Wolf	2015-02-14
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*	Added "check" command	Clifford Wolf	2015-02-13
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*	Some test related fixes	Clifford Wolf	2015-02-12
\| \| \| \|	(incl. removal of three bad test cases)
*	Added "make mklibyosys", some minor API changes	Clifford Wolf	2015-02-01
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*	Added "fsm -encfile"	Clifford Wolf	2015-01-30
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*	Added $equiv cell type	Clifford Wolf	2015-01-19
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*	Added cells.lib	Clifford Wolf	2015-01-16
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*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08
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*	Progress in memory_bram	Clifford Wolf	2015-01-03
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*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02
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*	New $mem simlib model	Clifford Wolf	2015-01-02
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*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30
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*	Fixed build with SMALL=1	Clifford Wolf	2014-12-30
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*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24
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*	Removed UTF-8 chars from techmap.v	Clifford Wolf	2014-12-12
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*	Added $dffe cell type	Clifford Wolf	2014-12-08
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*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08
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*	Added "abc" label in synth script	Clifford Wolf	2014-10-31
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*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31
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*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
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*	namespace Yosys	Clifford Wolf	2014-09-27
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*	Improvements in "synth" script	Clifford Wolf	2014-09-18
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*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16
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*	Added "synth" command	Clifford Wolf	2014-09-14
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*	Using alumacc in techmap.v	Clifford Wolf	2014-09-14
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*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08
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*	Simplified $fa undef model	Clifford Wolf	2014-09-08
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*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08
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*	Added $lcu cell type	Clifford Wolf	2014-09-08
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08
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*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
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*	Added $macc SAT model	Clifford Wolf	2014-09-06
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*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06
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