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Author
Age
*
Added adff2dff.v (for techmap -share_map)
Clifford Wolf
2014-08-07
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*
Implemented recursive techmap
Clifford Wolf
2014-08-03
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*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
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*
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf
2014-07-31
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*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
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*
New techmap default rules for $shr $sshr $shl $sshl
Clifford Wolf
2014-07-30
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*
Bugfix in simlib.v for iverilog
Clifford Wolf
2014-07-29
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*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
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*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
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*
Fixed simlib.v model for $mem
Clifford Wolf
2014-07-17
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*
Updated simlib to new $mem/$memwr interface
Clifford Wolf
2014-07-16
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*
Added SIMLIB_NOLUT to simlib.v
Clifford Wolf
2014-04-02
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*
Added SIMLIB_NOSR to simlib.v
Clifford Wolf
2014-04-02
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*
Added support for dlatchsr cells
Clifford Wolf
2014-03-31
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*
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
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(see https://github.com/cliffordwolf/yosys/pull/28)
*
Fixes for improved techmap of shifts with large B inputs
Clifford Wolf
2014-03-06
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Strictly zero-extend unsigned A-inputs of shift operations in techmap
Clifford Wolf
2014-03-06
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Improved techmap of shift with wide B inputs
Clifford Wolf
2014-03-06
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*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
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*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
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*
More changes to techlibs/common/simlib.v for LEC
Clifford Wolf
2014-01-31
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*
Added test comments to techlibs/cmos/cmos_cells.lib
Clifford Wolf
2014-01-29
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*
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
Clifford Wolf
2014-01-29
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*
Added $assert cell
Clifford Wolf
2014-01-19
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*
Fixed $lut simlib model for a wider range of tools
Clifford Wolf
2014-01-18
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*
More changes to simlib to make it friendlier to a wider range of tools
Clifford Wolf
2014-01-18
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*
Fixed a type in $mem model in simlib.v
Clifford Wolf
2014-01-18
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*
Removed cases of trailing comma in stdcells.v
Clifford Wolf
2014-01-18
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*
Added $bu0 cell to simlib.v
Clifford Wolf
2014-01-18
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*
Added techlibs/common/pmux2mux.v
Clifford Wolf
2014-01-17
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*
Various small cleanups in stdcells.v techmap code
Clifford Wolf
2013-12-31
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*
Added $bu0 cell (for easy correct $eq/$ne mapping)
Clifford Wolf
2013-12-28
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*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
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*
Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
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*
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
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*
Added "techmap -share_map" option
Clifford Wolf
2013-11-24
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*
Fixed xilinx/example_sim_counter test bench
Clifford Wolf
2013-11-24
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*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
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Updated abc
Clifford Wolf
2013-11-21
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Install simlib in datdir
Clifford Wolf
2013-11-19
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*
Added commented-out osu025 maping commands to cmos techmap example
Clifford Wolf
2013-11-18
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*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
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*
Fixed techmap of $reduce_xnor with multi-bit outputs
Clifford Wolf
2013-11-07
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Fixed techmap of $gt and $ge with multi-bit outputs
Clifford Wolf
2013-11-06
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*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
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Added DFFSR cell to techlibs/cmos/cmos_cells.lib
Clifford Wolf
2013-10-31
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[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
James Walmsley
2013-10-27
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Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
*
Cleanups in xilinx examples
Clifford Wolf
2013-10-27
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*
Added synth_xilinx command
Clifford Wolf
2013-10-27
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Moved simple xilinx counter sim example to subdir
Clifford Wolf
2013-10-27
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