Commit message (Expand) | Author | Age | ||
---|---|---|---|---|
... | ||||
* | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2013-07-09 | |
|\ | ||||
| * | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 | |
* | | Fixed shift ops with large right hand side | Clifford Wolf | 2013-07-09 | |
|/ | ||||
* | Fixed another bug found using vloghammer | Clifford Wolf | 2013-07-07 | |
* | Added defparam support to Verilog/AST frontend | Clifford Wolf | 2013-07-04 | |
* | Fixed a bug in AST frontend for cases with non-blocking assigned variables as... | Clifford Wolf | 2013-04-13 | |
* | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | Clifford Wolf | 2013-03-31 | |
* | Renamed hansimem.v test case to mem_arst.v | Clifford Wolf | 2013-03-24 | |
* | Added hansimem testcase (memory with async reset) | Clifford Wolf | 2013-03-24 | |
* | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 | |
* | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 | |
* | initial import | Clifford Wolf | 2013-01-05 |