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Age
*
Progress in Verific bindings
Clifford Wolf
2014-03-17
*
Progress in Verific bindings
Clifford Wolf
2014-03-14
*
Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)
Clifford Wolf
2014-02-19
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Added frontend (-f) option to autotest.sh
Clifford Wolf
2014-02-15
*
Updated ABC and some related changes
Clifford Wolf
2014-02-13
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Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)
Clifford Wolf
2014-02-12
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Removed old unused files from tests/
Clifford Wolf
2014-02-05
*
Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
Clifford Wolf
2014-02-03
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Added autotest.sh -p option
Clifford Wolf
2014-01-02
*
Use "abc -dff" in "make test"
Clifford Wolf
2013-12-31
*
Fixed commented out techmap call in tests/tools/autotest.sh
Clifford Wolf
2013-12-31
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
*
Added modelsim support to autotest
Clifford Wolf
2013-11-24
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Moved common techlib files to techlibs/common
Clifford Wolf
2013-09-15
*
Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
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Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
*
Improved vcdcd.pl (added -d option)
Clifford Wolf
2013-05-14
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Some improvements in vcdcd.pl
Clifford Wolf
2013-05-14
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added more .gitignore files (make test)
Clifford Wolf
2013-01-05
*
initial import
Clifford Wolf
2013-01-05