path: root/tests/tools
Commit message (Expand)AuthorAge
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-14
* Added and (tests/tools/...)Clifford Wolf2014-02-19
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
* Updated ABC and some related changesClifford Wolf2014-02-13
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
* Removed old unused files from tests/Clifford Wolf2014-02-05
* Replaced isim with xsim in tests/tools/, removed xst supportClifford Wolf2014-02-03
* Added -p optionClifford Wolf2014-01-02
* Use "abc -dff" in "make test"Clifford Wolf2013-12-31
* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-31
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Improved (added -d option)Clifford Wolf2013-05-14
* Some improvements in vcdcd.plClifford Wolf2013-05-14
* added more .gitignore files (make test)Clifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05